Hardware Design Verification Engineer 5 (Hybrid)

$169,437 - $190,237/Yr

Randstad - Redmond, WA

Full-time - Mid Level

Redmond, WA

Administrative and Support Services

About the position

The Hardware Design Verification Engineer 5 position is a contract role focused on verifying complex IP designs using advanced methodologies. The engineer will define verification strategies, create test plans, and lead verification efforts while collaborating with diverse teams. This role requires extensive experience in technical engineering, particularly in Universal Verification Methodology (UVM) and System Verilog, to ensure high-quality design outcomes.

Responsibilities

• Define verification strategy, requirements, and test environments for IP level verification.
• Create test plans and write tests to provide complete features coverage.
• Own verification for complex IPs, including creating test plans, developing UVM components and environments from scratch, writing test cases, debugging failures to root cause issues, running and maintaining regression suites, and closing coverage.
• Develop and implement technical solutions to complex quality and design challenges.
• Write scoreboards, sequences, constraints, assertions, and functional coverage.
• Write make files and scripts for verification infrastructure.
• Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment.
• Lead small teams of verification engineers and mentor engineers.
• Collaborate with teams across sites and geographies.

Requirements

• 10+ years of technical engineering experience OR a bachelor's degree in electrical engineering, Computer Engineering, or related field AND 5+ years of technical engineering experience OR a master's degree in electrical engineering, Computer Engineering, or related field AND 3+ years of technical engineering experience OR a Doctorate degree in Electrical Engineering, Computer Engineering, or related field.
• 7+ years of Technical Engineering Experience with Universal Verification Methodology (UVM), System Verilog, and Verification Fundamentals.
• In-depth knowledge of verification principles, testbenches, stimulus generation, and UVM based test environments.
• Solid understanding of computer architecture.
• Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments.
• Experience with scripting languages such as Python, Perl, or shell scripts.
• Prior experience with high performance DMA verification.

Nice-to-haves

• 10+ years of technical engineering experience OR a bachelor's degree in electrical engineering, Computer Engineering, or related field AND 8+ years of technical engineering experience OR a master's degree in electrical engineering, Computer Engineering, or related field AND 6+ years of technical engineering experience OR a Doctorate degree in Electrical Engineering, Computer Engineering, or related field AND 3+ years of technical engineering experience.
• Experienced in test plan development to define test cases, checkers, assertions, and functional coverage points.
• Experience in verification of many designs at unit level.
• Knowledge of verification principles, testbenches, UVM, and coverage.
• Knowledge of system verilog class, constraints, coverage, and assertions.
• Proficient communication, collaboration, and teamwork skills.

Benefits

• Health insurance
• 401K contribution
• Incentive and recognition program