Hardware Emulation Engineer

Enfabrica Corporation - Mountain View, CA

Full-time - Mid Level

Remote - Mountain View, CA

About the position

As a Hardware Emulation Engineer at Enfabrica, you will join a team of experts in silicon and distributed systems to develop innovative hardware emulation frameworks. This role focuses on building and maintaining emulation infrastructure for large-scale networking and computing chips, contributing to the validation of chip designs pre-silicon, and enhancing emulation methodologies to improve robustness and efficiency. You will work collaboratively across various teams to address infrastructure challenges and support the development of next-generation distributed computing systems.

Responsibilities

• Collective ownership of emulation build infrastructure.
• Collective ownership of chip level emulation models.
• Collective ownership of tools around build automation, run automation and debug utilities.
• Development and ownership of Github based CI/CD flows for emulation code base.
• Own and maintain emulation infrastructure.
• Own and maintain chip level emulation models for validating different subsystems within a networking chip.
• Work with vendors on hardware and tool issues on a need basis.
• Enhance emulation methodology for robustness, test throughput, portability and debuggability.
• Work cross functional with simulation, firmware and software test team to validate the chip pre-silicon.
• Support SW test bring up and debug on hardware emulator, collaborate with hardware design team to triage and fix design issues.
• Leverage understanding of simulation based design verification flows to help emulation test-planning and execution.
• Work cross functional with simulation, firmware and software test team to repro failures seen in real silicon on the emulator.

Requirements

• Emulation experience on any of the emulation platforms: Palladium, Zebu or Veloce.
• Experience with emulation compile flow, wave dump & triggers, waveform debug, running tests.
• Experience writing scripts in Perl or Python.
• Exposure to Makefile, Bazel or other build flows.
• Experience with waveform debug tools such as Verdi/SimVision/Indago.
• Good understanding of Verilog and SystemVerilog RTL design.
• Exposure to synthesizable SystemVerilog/Verilog code and SVAs.
• Strong communication skills and a team player.
• MS with 5+ years of experience, BS with 7+ years experience.

Nice-to-haves

• Working knowledge of PCIE, Ethernet, AXI, DDR, etc.
• Working knowledge of UART, SPI, JTAG, QSPI, etc.
• Working knowledge of ARM based processors.
• Exposure to Design Verification and System Verilog, UVM, and C/C++ verification environments.

Benefits

• Flexible work location (remote options available)
• Opportunity to work in a fast-paced startup environment
• Collaboration with a team of experienced professionals
• Potential for career growth in a cutting-edge technology field