Hardware Engineer (FPGA)

About the position

Virtu is a leading financial firm that leverages cutting edge technology to deliver liquidity to the global markets and innovative, transparent trading solutions to our clients. As a market maker, Virtu provides deep liquidity that helps to create more efficient markets around the world. Our market structure expertise, broad diversification, and execution technology enables us to provide competitive bids and offers in over 19,000 securities, at over 235 venues, in 36 countries worldwide. The Virtu Financial Hardware Design team is responsible for the design, verification, and deployment of many complex FPGA applications. This technology forms part of the firm's proprietary, low latency trading platform. The environment and being a part of this team presents stimulating, challenging and rewarding work within a collaborative, international work environment. We are looking for an FPGA Engineer to join the hardware team. The ideal candidate will be a creative and ambitious senior hardware engineer excited to work on the design and verification of our low latency trading infrastructure.

Responsibilities

• Enhancing the company's capabilities in Hardware system design and verification
• Developing solutions for demanding problems
• Contributing to complex aspects of the project
• Providing a leading role in defining the technical basis for future products
• Innovating and introducing new solutions and methods
• Planning, scheduling and execution of projects

Requirements

• Academic degree in Electrical or Computer Engineering
• Minimum 2 years of work experience preferred. Advanced degree may be a substitute for experience
• Successful track record in hardware projects, FPGA or ASIC
• Demonstrated experience in complex verification environment in Systemverilog, UVM, OVM, VMM
• Expertise in IC Design flows, specifications, Verilog or VHDL
• Good knowledge of high performance bus protocols, for example AXI, USB, SATA, PCIe, etc.
• Strong problem solving and communication skills

Nice-to-haves

• Any experience of embedded C/C++ development is beneficial
• Previous experience with Constrained Random Verification a plus