Hardware Engineer Intern - ASIC design and logic verification 2025

IBM - San Jose, CA

Part-time - Intern

San Jose, CA

Computer and Electronic Product Manufacturing

About the position

The Hardware Engineer intern position at IBM T. J. Watson Research Center offers students the opportunity to work on the design and development of next-generation AI compute chips and network interconnect technologies. Interns will collaborate with a team of scientists and engineers to write VHDL/Verilog modules for AI Accelerator SoCs and perform functional verification of design modules, contributing to the advancement of AI technology.

Responsibilities

• Write VHDL/Verilog modules for the AI Accelerator SoC.
• Perform functional verification of design modules.
• Develop tests for functional logic verification.
• Evaluate system performance and provide feedback to system architects and logic design engineers.

Requirements

• Experience in ASIC or FPGA logic verification.
• Strong FPGA/ASIC RTL logic design skills.
• Experience with programming in C, C++, and Python.
• Knowledge of computer architecture and system design.
• Bachelor in Computer Engineering, Electrical Engineering or related fields.

Nice-to-haves

• 1 year or more experience in Verilog/VHDL logic verification.
• Experience with custom-hardware for AI/ML.
• Experience in network interconnect architectures.
• Familiarity with Foundation Models / Large Language Models.
• In later years of a Master degree program in a related field.

Benefits

• Paid family medical leave
• Disability benefits
• Employee Stock Purchase Plan
• Paid holidays
• Paid sick time