Hardware PCB CAD Layout Engineer

Apple - Beaverton, OR

Full-time

Beaverton, OR

Computer and Electronic Product Manufacturing

About the position

The Hardware PCB CAD Layout Engineer at Apple is responsible for designing high-density printed circuit boards (PCBs) for next-generation, high-performance, power-efficient System on Chips (SoCs). This role involves collaborating with cross-functional teams to create detailed layouts of rigid and flexible PCBs, utilizing advanced PCB CAD applications and tools. The engineer will also explore new technologies and ensure that designs meet manufacturing and assembly standards, impacting a wide range of Apple products.

Responsibilities

• Design and layout high density printed circuit boards (PCBs) using Cadence Allegro.
• Design from early placement through routing and final rule checks.
• Place high density and high quantity (up to 10000+) of components.
• Incorporate Design for Manufacturing (DFM), Design for Assembly (DFA), and Design for Test (DFT) principles throughout the product development lifecycle.
• Communicate effectively with cross-functional teams to ensure the highest quality PCB designs.
• Generate constraints based on schematic interpretation, design rules, manufacturing rules, and mechanical specifications.
• Resolve PCB design issues with fabrication and manufacturing vendors.
• Provide complex input into the PCB design specifications and standards with respect to manufacturing capabilities, design limitations, and design limitations to determine trade-offs necessary to meet goals and produce high quality PCBs within schedule.

Requirements

• Thorough and extensive understanding of Cadence Allegro, including all aspects of Constraint manager, importing/exporting of varying file types, design details, and processes.
• Experience in designing high-density PCBs with a high quantity of components.
• Strong communication skills to collaborate with cross-functional teams.
• Knowledge of Design for Manufacturing (DFM), Design for Assembly (DFA), and Design for Test (DFT) principles.