Google - Mountain View, CA

posted 7 months ago

Full-time - Mid Level
Mountain View, CA
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About the position

As an Integration Methodology and Flow Physical Design Engineer at Google, you will be at the forefront of designing and building the hardware that powers Google's vast array of services. Your role will involve tackling complex computational challenges that require custom hardware solutions rather than off-the-shelf products. You will work on the integration of System-on-a-Chip (SoC) designs, focusing on low power design methodologies and ensuring that the integration flows are efficient and effective. This position requires a deep understanding of physical design flows and the ability to develop and execute SoC integration strategies that meet stringent performance, power, and area requirements. In this role, you will lead projects that span multiple engineering domains within a data center facility. This includes overseeing the construction and installation of equipment, troubleshooting issues, and collaborating with vendors to ensure that all systems are functioning optimally. Your technical expertise will be crucial in developing new technologies and hardware that enhance computing capabilities, making them faster and more powerful. You will also be responsible for ensuring that the SoC integration is block-friendly and aligns with the overall design goals, including reliability and performance metrics. Your work will have a significant impact on the machinery that supports Google's cutting-edge data centers, ultimately affecting millions of users worldwide. You will be part of a team that combines the best of AI, software, and hardware to create innovative solutions that improve people's lives through technology. This position offers a unique opportunity to contribute to the development of systems that are integral to Google's mission of organizing the world's information and making it universally accessible and useful.

Responsibilities

  • Develop, support and execute SoC integration flow development and execution, including multiple scenarios of die size planning, bump planning, IO and block placements, power regions planning, layout routing planning, and product graphics grid with multiple power regions.
  • Be responsible for bump/micro-bump to package integration planning and implementation of package driven feedback into high-level designs.
  • Ensure SoC integration is block friendly, easy to implement, and meets power, performance, and area goals.
  • Ensure multiple power domains Electromigration/Voltage (EM/IR) and bump planning will meet reliability requirements.
  • Own and drive execution of high-level SoC and partner with foundry to resolve issues related to new technologies.

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 5 years of experience with SoC Integration focused on low power design.
  • Experience with new process technology based SoC integration flow development and tape-out.
  • Experience with scripting languages (i.e., Python, Bash, Tcl) for workflow automation and data visualization.
  • Experience with physical design flow development and design closure for multiple ASIC/SoCs.

Nice-to-haves

  • Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
  • Experience in System-on-a-Chip (SoC) integration, including 2.5D and 3 Dimensional Integrated Circuit integration and sign-off.
  • Experience in extraction of ASIC design parameters, Quality of Results (QoR) metrics, and analyzing trends.
  • Experience in co-optimization to enable schedule sensitive development with consideration of block complexity, power domains, clocking, congestion, etc.

Benefits

  • Competitive salary range of $150,000-$223,000 based on experience and location.
  • Bonus and equity options available.
  • Comprehensive health insurance coverage.
  • Retirement savings plan with 401(k) options.
  • Generous paid time off and holidays.
  • Opportunities for professional development and continued education.
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