About the position
As an Intern - Design Verification at Micron Technology, Inc., you will play a crucial role as a technical individual contributor in the design and validation of the on-chip controller and mixed signal circuitry in NAND FLASH chips. This position is highly visible and presents a challenging opportunity to engage in various aspects of design verification. Your responsibilities will encompass the development of test plans and verification processes, including RTL design verification of the controller hardware, verification of firmware code for NAND internal operations, and full-chip Verilog verification. In this role, you will contribute to the development of a Random sequence test bench by reviewing block-level specification documents for both new and legacy features. You will also be responsible for developing and supporting System Verilog Assertions (SVA) test benches to perform sub-system and full-chip Verilog verification. Additionally, you will conduct RTL code coverage and review functional coverage bins to achieve coverage goals. Your expertise will be essential in implementing, enhancing, and supporting multiple automation tools to improve design verification efficiency, utilizing scripting languages such as PERL and Python. Moreover, you will engage in verification processes that involve modeling and simulation using industry-standard simulators. Effective communication across groups will be vital as you work towards standardization and contribute to the overall success of the team.
Responsibilities
- Contribute towards Random sequence test bench development by reviewing block level spec documents for new and legacy features
- Develop and support SVA (System Verilog Assertions) Test Bench to perform sub-system and full chip Verilog verification
- Perform RTL Code coverage and review Functional Coverage bins to achieve coverage goals
- Implement/Enhance/Support multiple automation tools to improve DV efficiency (PERL, Python)
- Perform verification processes with modeling and simulation using industry standard simulators
- Contribute to cross group communication to work towards standardization and group success
Requirements
- Proficiency in System Verilog/SVA/Verilog is preferred
- Good understanding of scripting languages PERL, Python, Tcl, Csh
- Bachelor's Degree with 5+ years of Design experience or Master's Degree in Electrical Engineering with 3+ years of experience
Benefits
- Choice of medical, dental and vision plans
- Benefit programs that help protect income due to illness or injury
- Paid family leave
- Robust paid time-off program
- Paid holidays
