Interposer Physical Design Engineer

$177,000 - $266,000/Yr

Google - Sunnyvale, CA

Full-time - Senior

Sunnyvale, CA

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About the position

As an Interposer Physical Design Engineer at Google, you will be part of a diverse team dedicated to developing custom silicon solutions that enhance Google's direct-to-consumer products. This role involves shaping the next generation of hardware experiences, focusing on performance, efficiency, and integration. You will contribute to the architecture that supports Google's product portfolio, ensuring optimal functionality and user experience.

Responsibilities

• Own interposer routing necessary for 2.5D or 3D packaging (i.e., custom signal routing, shielding and power/ground distribution).
• Connect general purpose and high speed interfaces through an interposer with consideration for high speed effects, signal integrity, etc.
• Perform Application-Specific Integrated Circuit (ASIC) top level I/O planning and Redistribution Layer (RDL) routing.
• Perform technical evaluations of interposers, advanced packaging, process nodes, IP and provide recommendations.
• Collaborate with other design teams, including ASIC designers, package designers, and system architects on interposer layout and specification requirements, collaterals, and milestone timelines.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in ASIC physical design flows and methodologies in advanced process nodes.
• Experience with routing through custom routing or PnR tool routing.
• Experience with layout, physical verification, Design for Manufacturability (DFM), power and signal integrity analysis using industry standard tools.
• Experience with Controlled-Collapse Chip Connection (C4) bumps, micro bumps, Deep Trench Capacitor (DTC), Through-silicon via (TSV) etc.

Nice-to-haves

• Experience with leading one or more aspects of interposer or package design.
• Experience in extraction of design parameters, Quality of Results (QoR) metrics, and analyzing trends.
• Knowledge of techniques for testing and debugging interposer designs, including electrical and thermal.
• Knowledge of semiconductor device physics and transistor characteristics.
• Understanding of thermal considerations for 3D stacked dies and interposers.

Benefits

• Competitive salary range of $177,000-$266,000 + bonus + equity + benefits.
• Comprehensive health insurance coverage.
• Retirement savings plan with 401(k) options.
• Generous paid time off and holidays.
• Opportunities for professional development and continued education.