Lead IC Verification Application Engineer

$120,400 - $223,600/Yr

Cadence Design Systems

Full-time - Mid Level

Professional, Scientific, and Technical Services

About the position

The Application Engineer role at Cadence involves working closely with customers to provide technical support and innovative solutions for verification challenges using Cadence's advanced verification platforms. This position is integral to the North America Verification Field Applications Engineering Team, focusing on customer success and collaboration with R&D to enhance verification methodologies and tools. The role offers opportunities for career advancement in technical, management, or sales/marketing tracks.

Responsibilities

• Establish technical credibility and rapport with the customer and become the go-to expert for all of their technical inquiries and support.
• In collaboration with R&D, provide in-depth technical assistance to help support advanced verification flows to secure design wins.
• Champion the customer needs and work closely with R&D and marketing to develop competitive and creative technical solutions.
• Understand the competitive landscape and continuously work on differentiating Cadence's solutions.
• Write technical product literature such as application notes and technical articles.
• Review new product proposals and device specifications.
• Assume technical leadership roles in small teams as needed.

Requirements

• 5+ years experience with SystemVerilog, VHDL, Verilog.
• BS, MS, or PhD degree in Computer Science/Engineering, Electrical Engineering, or related field.
• Verification skills such as UVM testbench architecture, development and debug.
• Strong RTL and Testbench debug skills.
• Experience in writing scripts (Perl, Python or Tcl).
• Strong software, HDL design and verification skills.
• Ability to quickly analyze verification environments and design complexity.
• Strong verbal and written communication skills.
• Strong teamwork skills.
• Ability to interact effectively with both external customers and R&D teams.

Nice-to-haves

• Experience with C/C++/SystemC.
• Experience in deploying VIP in testbenches.
• Knowledge of protocols like JTAG, UART, PCIe, AMBA, DDR.
• Knowledge of design fundamentals such as architecture, micro-architecture, HDLs and Synthesis and timing.
• Digital design experience.

Benefits

• Paid vacation and paid holidays.
• 401(k) plan with employer match.
• Employee stock purchase plan.
• A variety of medical, dental and vision plan options.