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Talentburst - Cupertino, CA

posted 2 months ago

Full-time - Mid Level
Cupertino, CA
Administrative and Support Services

About the position

The Mask Layout Designer III will play a crucial role in the design and layout of RF, analog, and mixed-signal blocks for complex SoC products. This position involves working closely with a world-class engineering team to develop state-of-the-art designs that will be integrated into a wide range of products, impacting user experience significantly. The role requires expertise in detailed transistor-level layout and verification processes, ensuring high-quality designs that meet industry standards.

Responsibilities

  • Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, Client/DAC, baseband filters, and bandgap/bias/LDO.
  • Block level layout through full verification flow including extraction, DRC, LVS, and DFM checking.
  • Co-work with designers on block level floorplanning.
  • Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.

Requirements

  • BS degree in a relevant field.
  • 5+ years of relevant industry experience.
  • Experience with FinFet technology.

Nice-to-haves

  • Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS.
  • Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing.
  • Solid understanding of RC delay, electromigration, and coupling.
  • Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE, etc.
  • High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. in FinFet Technology (7nm experience highly preferred).
  • Knowledge of CADENCE layout tools.
  • Scripting skills in PERL or SKILL.
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