Memory Controller Micro-Architect/Logic Designer (Contractor)

$90 - $120/Yr

Samsung Electronics America - San Jose, CA

Hybrid - San Jose, CA

Merchant Wholesalers, Durable Goods

About the position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!

Responsibilities

• Drive the timely development and debug of new features on timely development of custom memory controller.
• Work on SOC IP delivery with all sanity checks.
• Work on timing debug and closure.
• Work on LINT, CDC flows and analysis, and ECO flows.
• Work on power artist flow and power analysis.
• Coordinate with the verification team to verify the functionality and correctness of the design.
• Collaborate with implementation teams to achieve timing and area.
• Produce quality RTL on schedule meeting PPA goals.
• Engage with performance and power team on achieving performance and power goals.
• Partner with the physical design and CAD team to resolve implementation level details.

Requirements

• 10+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master's degree, or 6+ years of experience with a PhD.
• Strong background owning and driving the RTL design of various sub-blocks of custom memory controller designs.
• Demonstrated experience of successful Architectural through RTL design experience on high performance digital designs.
• Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis & ECO.
• Knowledge of memory controller u-architecture.
• Familiarity with different memory technologies like LPDDR4/5, HBM.
• Knowledge of JEDEC memory standards preferred.
• Knowledge of AES, ECC, RAS features preferred.
• Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.
• Experience with a scripting language like Perl or Python.
• Energetic, curiosity, and passion in logic design.
• Good written and verbal communication skills.

Benefits

• The hourly rate range for this role is between $90 and $120 per hour.