MTS | DMTS - HBM SOC Design & Integration Engineer

About the position

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence. As a MTS | DMTS HBM SOC Design and Integration Engineer, you will be responsible for the design & development of next-generation HBM DRAM products. You will collaborate closely with a distributed team of Design Engineering, Product Engineering, Process Development, Package Engineering & Business Units to ensure the success of our future HBM roadmap. Your role will involve applying your deep understanding of SOC Architecture, RTL Logic Design, IP Integration, high-speed interface design, and high-performance computing architectures to analyze bottlenecks and propose innovative architectures for Micron’s HBM product portfolio. The HBM technology pertains to stacking DRAM chips along with a logic chip within one package through TSV (Through Silicon Via), increasing memory density and allowing high-speed signal transmission. The verification and testing of HBM are challenging due to the design's size and complexity, making this role uniquely exciting. Our team vision is to develop your skills in an inclusive, diverse environment of multicultural teams across worldwide geographies.

Responsibilities

• Analyze customer requirements and specification documents.
• Work with IP vendors to select off-the-shelf IPs and modify or custom design new ones if needed.
• Review architectural specifications and provide constructive feedback.
• Efficiently execute project deliverables, including writing specifications, developing RTL, integrating IP, testing code, debugging failures, and running static checks.
• Proactively identify quality issues, performance problems, and opportunities to reduce power consumption.
• Collaborate with the verification team by reviewing test plans and providing feedback for test changes.
• Debug and identify root causes and solutions for pre-silicon and post-silicon issues.
• Engage with customers to support issues with current HBM architectures.

Requirements

• 10+ years of relevant job/skill-related experience.
• Proficiency in microarchitecture and high-quality RTL development with the ability to write and test code in System Verilog.
• Experience with automating IP integration using standards such as IP-XACT and tools such as Coretools, Defacto.
• Experience with using register description languages such as SystemRDL.
• Experience with SOC integration methods such as DFT/MBIST, CDC, and static LP checks.
• Experience dealing with clock domain crossings (CDC).
• Experience with SOC interconnects and bus standards like AMBA AXI, ACE, APB, AHB.
• Ability to write assertions using SVA.
• Understanding of design optimization for performance and low power consumption.
• Good knowledge of static timing analysis and synthesis design constraints.

Nice-to-haves

• BSEE or higher.
• Familiarity with DRAM operation and JEDEC specifications, preferably with the HBM product family.
• Familiarity with scripting languages such as Python.
• Experience with working on IPs like UCIE, Memory Controller, NOCs.
• Experience in memory array architectures, high-speed signaling, PHY & interface development, power delivery network planning, and thermal modeling.

Benefits

• Medical, dental, and vision plans.
• Income protection programs for illness or injury.
• Paid family leave.
• Robust paid time-off program and paid holidays.
• Discretionary bonuses and equity options.