PCIe/CXL SOC Lead

AMD - San Jose, CA

Full-time - Senior

San Jose, CA

Computer and Electronic Product Manufacturing

About the position

The PCIe/CXL SOC Lead at AMD is a senior design micro-architect and team leader responsible for driving the development of next-generation high-performance PCIe/CXL connectivity solutions. This role involves collaboration with various engineering teams to ensure successful project completion and first-pass silicon success, while fostering an inclusive and innovative work environment.

Responsibilities

• Participate in the definition of microarchitecture of next-generation high-performance PCIe/CXL connectivity solutions.
• Lead a team of hardware engineers, responsible for milestone and scheduled delivery to various teams.
• Execute on RTL design and coding for various sections of the SOC.
• Contribute to silicon debug and product support as needed.

Requirements

• Strong experience with PCIe and CXL.
• Proven experience in RTL design, Verilog, and System Verilog.
• Deep knowledge of front-end tools such as Verilog simulators, linters, and clock-domain crossing checkers.
• Validated experience with synthesis, static timing, DFT, and ECO is a plus.
• Exposure to physical design and verification methods.
• Experience with scripting languages including Perl, Python, Unix shells, and Makefiles.
• Strong communication, collaboration, and presentation skills.

Nice-to-haves

• Experience mentoring and leading a team through successful project completion.
• Passion for modern, complex microarchitecture and digital design.

Benefits

• Employee stock purchase plan
• Annual bonus or sales incentive eligibility
• Competitive benefits package