PHY Design Verification Engineer

$143,100 - $264,200/Yr

Apple - Cupertino, CA

Full-time - Mid Level

Cupertino, CA

Computer and Electronic Product Manufacturing

About the position

Join Apple's dynamic wireless silicon development team, where you will play a pivotal role in the design and verification of wireless systems on a chip (SoC). Our wireless SoC organization is dedicated to creating highly energy-efficient designs and innovative technologies that enhance user experiences at the product level. This is achieved through a world-class vertically integrated engineering team that encompasses various disciplines, including RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and Firmware/Software engineering. In this highly visible position, you will be at the heart of a silicon design group that significantly impacts the rapid delivery of functional wireless products to hundreds of millions of customers. In this role, you will collaborate closely with the system and design teams to review and comprehend the PHY subsystem microarchitecture. You will be responsible for creating verification plans based on specifications and building block/subsystem level test benches using best-in-class design verification methodologies. Your work will involve architecting test benches with a focus on maximum reusability, developing and executing both directed and constrained random tests, debugging failures, managing bug tracking, and working with designers to ensure the closure of identified issues. Additionally, you will create and analyze block/subsystem level coverage models and add test cases to enhance coverage. Supporting PHY subsystem validation using Palladium and FPGA will also be part of your responsibilities.

Responsibilities

• Work closely with system/design team to review and understand PHY subsystem microarchitecture and create verification plans from specifications.
• Build block/subsystem level test benches with reference model, using best in class DV methodology.
• Architect test benches with maximum reusability in mind.
• Develop and execute both directed and constrained random tests, debug failures, manage bug tracking, and work with designers to drive closure of issues found.
• Create and analyze block/subsystem level coverage model, and add test cases to increase coverage.
• Support PHY subsystem validation using Palladium and FPGA.

Requirements

• BS degree in a relevant field and 3+ years of industry experience.
• Verification experience of wireless/wired communication block/subsystem.
• Excellent knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage.
• Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
• Experience of using Matlab/C reference model and bit-accurate verification is a plus.
• Knowledge of wireless protocols such as Bluetooth, WLAN, or Zigbee is a plus.
• Proficiency in shell and Perl scripting; Python skills are a plus.
• Experience of Palladium/FPGA validation is a plus.
• Strong team player with excellent communication skills, self-motivated and well organized.

Nice-to-haves

• Experience with Matlab/C reference model and bit-accurate verification.
• Knowledge of wireless protocols such as Bluetooth, WLAN, or Zigbee.
• Proficiency in shell and Perl scripting; Python skills.

Benefits

• Comprehensive medical and dental coverage
• Retirement benefits
• Discounted products and free services
• Reimbursement for certain educational expenses, including tuition
• Opportunity to participate in Apple's discretionary employee stock programs
• Eligibility for discretionary bonuses or commission payments
• Relocation assistance if applicable.