Principal Analog Design Engineer

$130,400 - $223,000/Yr

OSI Engineering - Agoura Hills, CA

Full-time - Senior

Agoura Hills, CA

Administrative and Support Services

About the position

The Principal Analog Design Engineer will play a crucial role in the Bufferchip Design team, focusing on the development of innovative analog designs that enhance data speed and security. This position involves collaboration with top engineers and inventors, taking ownership of designs, and mentoring junior designers.

Responsibilities

• Take full ownership of analog designs at the chip and/or block level.
• Define optimal architectures to meet competitive product specifications.
• Design, simulate, and characterize high-performance and high-speed circuits, including transmitters, receivers, ADCs, DACs, LDOs, PLLs, DLLs, and PI circuits.
• Develop high-level models for design tradeoff analysis and behavioral models for verification simulations.
• Create floorplans and collaborate with the layout team to ensure post-extraction performance meets specifications.
• Document analysis and simulations to validate that designs achieve critical electrical and timing parameters as part of the pre-silicon verification flow.
• Work with the Lab/System team on test plans, silicon bring-up, and characterization.
• Understand and communicate applicable standards and their relevance to projects within the team.
• Mentor junior designers to foster skill development and knowledge sharing.

Requirements

• MS in Electrical Engineering with 5+ years of experience or a PhD in Electrical Engineering with 2+ years of experience in CMOS analog circuit design.
• Experience and in-depth knowledge of Advantest V93k required.
• Prior experience in designing at least one of the following circuits: transmitter, receiver (including CTLE, DFE), PLL, DLL, PI, or clock distribution.
• Strong understanding of design principles and practical design tradeoffs.
• Fundamental knowledge of basic building blocks such as bias circuits, op-amps, and LDOs.
• Experience with memory interfaces like DDR4/5 or serial links such as PCIe is highly desirable.
• Prior design experience in FinFET processes and digitally-assisted design is a plus.
• Experience in modeling with MATLAB, Verilog-A, or Verilog is desirable.
• Experience in leading R&D and future technology development projects is a plus.
• Strong written and verbal communication skills, along with the ability to work effectively in cross-functional and globally dispersed teams.

Nice-to-haves

• Experience with memory interfaces like DDR4/5 or serial links such as PCIe is highly desirable.
• Prior design experience in FinFET processes and digitally-assisted design is a plus.
• Experience in modeling with MATLAB, Verilog-A, or Verilog is desirable.
• Experience in leading R&D and future technology development projects is a plus.