Principal Application Engineer

$120,400 - $223,600/Yr

Cadence Design Systems - San Jose, CA

Full-time - Principal

San Jose, CA

Professional, Scientific, and Technical Services

About the position

At Cadence, we hire and develop innovators and leaders who want to make an impact on the world of technology. The ideal candidate will be energetic, innovative, and enthusiastic about helping customers solve their toughest verification problems using Cadence technology. As an integral member of the North America Verification Field Applications Engineering (AE) Team, you will work directly with industry-leading semiconductor and system companies to deploy Cadence's market-leading verification platforms, including cutting-edge technologies such as Portable Stimulus Standard and machine learning. In this customer-facing role, you will provide front-line technical support in the pre and post-sales process and collaborate with the account team to devise innovative solutions to address our customers' most challenging verification problems. You will own customer success!

Responsibilities

• Develop customer-specific verification requirements, including advanced verification component development, methodology support, and operation and maintenance of Cadence's verification tools and services.
• Support technical evaluations and benchmark development for Cadence's market-leading tools such as Xcelium simulation platform, vManager verification management platform, and Perspec portable stimulus system.
• Create and conduct technical presentations and product demonstrations for customers.
• Establish technical credibility and rapport with the customer and become the go-to expert for all of their technical inquiries and support.
• In collaboration with R&D, provide in-depth technical assistance to help support advanced verification flows to secure design wins.
• Champion customer needs and work closely with R&D and marketing to develop competitive and creative technical solutions.
• Write technical product literature such as application notes and technical articles.
• Review new product proposals and device specifications.
• Assume technical leadership roles in small teams as needed.

Requirements

• BS, MS, or PhD degree in Computer Science/Engineering, Electrical Engineering, or related field.
• 5+ years experience with SystemVerilog, VHDL, Verilog.
• Verification skills such as UVM testbench architecture, development, and debug.
• Strong RTL and Testbench debug skills.
• Experience in writing scripts (Perl, Python, or Tcl).
• Strong software, HDL design, and verification skills.
• Ability to quickly analyze verification environments and design complexity.
• Strong verbal and written communication skills.
• Strong teamwork skills.
• Ability to interact effectively with both external customers and R&D teams.

Nice-to-haves

• Experience with C/C++/SystemC.
• Experience in deploying VIP in testbenches.
• Knowledge of protocols like JTAG, UART, PCIe, AMBA, DDR.
• Knowledge of design fundamentals such as architecture, micro-architecture, HDLs, and Synthesis and timing.
• Digital design experience.

Benefits

• Paid vacation and paid holidays
• 401(k) plan with employer match
• Employee stock purchase plan
• A variety of medical, dental, and vision plan options