Principal Design Engineer – RTL Design & Integration

About the position

As a Principal Design Engineer, you will play a key role in defining and integrating architectures for Celestial AI's IP and SOCs, focusing on high-speed interfaces and chip interconnect solutions. You will collaborate closely with system architects, RTL designers, and verification teams to develop high-performance SoC designs. This role requires deep expertise in RTL design, integration, and memory subsystem architectures.

Responsibilities

• Architect, design, and integrate high-performance SoC components, including high-speed memory interfaces (e.g., DDR, HBM) and chip interconnects (e.g., AXI, NoC, UCIe, CXL, PCIe).
• Develop and implement complex RTL designs using SystemVerilog, ensuring scalability, power efficiency, and reusability.
• Lead SoC-level integration efforts, working closely with cross-functional teams on design specifications, IP integration, and performance optimization.
• Define synthesis constraints for modules and SOC and collaborate with Synthesis and Physical Design teams.
• Author detailed design specifications and documentation for SoC modules and subsystems.
• Collaborate with verification engineers to define test strategies, drive coverage closure, and ensure functional correctness.
• Optimize for power, performance, and area (PPA) by evaluating tradeoffs at both module and SoC levels.
• Perform static and dynamic analysis using industry-standard tools (Lint, CDC, STA, and LEC) to ensure high-quality designs.
• Provide technical leadership and mentorship to junior engineers and cross-functional teams.

Requirements

• MS or PhD in Electrical Engineering, Computer Engineering, or a related field preferred.
• 8+ years of experience in SoC design, RTL development, and integration.
• Expertise in RTL design using SystemVerilog.
• Strong understanding of high-speed memory interfaces (e.g., DDR, HBM) and chip-to-chip interconnects (e.g., AXI, UCIe, PCIe, CXL).
• Strong knowledge of RTL verification and validation methodologies, including Lint, CDC, STA, and LEC.
• Experience with low-power design techniques, including clock gating, power gating, and voltage scaling.
• Deep understanding of SoC architecture, including multi-core processing, coherency protocols, and subsystem integration.
• Proficiency with SoC design tools, including simulation, synthesis, timing analysis, and power estimation.
• Working knowledge of formal verification methodologies (SVA, UVM).
• Experience with scripting languages (Python, Perl, TCL) for design automation.

Benefits

• Competitive base salary.
• Bonus.
• Generous grant of early-stage equity.
• Health insurance.
• Vision insurance.
• Dental insurance.
• Life insurance.
• Collaborative and continuous learning work environment.