Principal Engineer-ASIC Design (Integration)

$75,000 - $232,000/Yr

Microchip Technology - San Jose, CA

Full-time - Senior

San Jose, CA

10,001+ employees

Computer and Electronic Product Manufacturing

About the position

As a Principal Engineer in ASIC Design (Integration) at Microchip Technology, you will play a pivotal role in the design, integration, and verification support of Full Chip Architecture and Full Chip Control/Data buses for advanced ASIC or FPGA projects. Your primary responsibility will be to ensure seamless integration of various components on the device, which includes working closely with multiple design teams. You will be involved in detailed module design and integration, performance analysis, and the creation of detailed design specifications. A significant part of your role will also involve the documentation of the SOC or FPGA device and/or device family, ensuring that all aspects of the design are thoroughly recorded and communicated. You will participate in the Verilog implementation and integration of full chip capabilities, including interface support and the integration of full chip buses (control and data network-on-chip). Your expertise will be crucial in supporting full chip post-layout timing closure and verification, as well as investigating and assessing legacy and emerging integration techniques. You will also be responsible for improving data and command processing bandwidth, reducing latencies, and increasing reliability. Additionally, you will support the porting of designs into test chips and emulation platforms, as well as pre-tapeout verification and post-tapeout validation/characterization of the designed systems. Collaboration is key in this role, as you will work closely with FPGA support software and firmware engineers to resolve hardware and customer issues. Your strong technical leadership will be essential in guiding the team towards successful project outcomes, while your ability to communicate effectively will ensure that all stakeholders are aligned throughout the design and integration process.

Responsibilities

• Design, integration, and verification support of Full Chip Architecture and Full Chip Control/Data buses for ASIC or FPGA.
• Conduct detailed module design and integration, performance analysis, and create detailed design specifications.
• Ensure seamless integration of all components on the device by collaborating with design teams.
• Document full chip specifications for SOC or FPGA devices and device families.
• Participate in Verilog implementation and integration of full chip capabilities, including interface support and network-on-chip integration.
• Support full chip post-layout timing closure and verification processes.
• Investigate and assess legacy and emerging integration techniques and on-chip/off-chip network-on-chip bus structures.
• Improve data and command processing bandwidth, reduce latencies, and increase reliability.
• Support porting designs into test chips and emulation platforms.
• Assist in pre-tapeout verification and post-tapeout validation/characterization of the designed systems.
• Collaborate with FPGA support software and firmware engineers to resolve hardware and customer issues.

Requirements

• Minimum of 10 years of proven silicon design experience in system level integration of various ASIC IP blocks.
• Experience in SOC IP development and Full Chip Integration.
• Strong technical leadership skills and ability to work in a team-oriented environment.
• Proficient in Verilog design and design verification.
• Strong experience in Static Timing Analysis and Verilog simulation tools.
• Ability to write detailed design specifications and clean, readable presentations.
• Good analytical, oral, and written communication skills.
• Self-motivated and proactive team player.
• Ability to work to schedule requirements.

Nice-to-haves

• Experience with high-speed data network-on-chip (NOC) buses.
• Familiarity with legacy integration techniques and emerging technologies in ASIC design.

Benefits

• Competitive base pay and restricted stock units.
• Quarterly bonus payments.
• Health benefits starting from day one.
• Retirement savings plans.
• Industry-leading Employee Stock Purchase Plan (ESPP) with a 2-year look back feature.