Principal Engineer - Design

$70,000 - $163,000/Yr

Microchip Technology Incorporated - Roseville, CA

Full-time - Senior

Roseville, CA

10,001+ employees

Computer and Electronic Product Manufacturing

About the position

The successful candidate will join the rapidly growing Data Center Solutions (DCS) business unit at Microchip. DCS has a broad portfolio of products widely deployed by the industry's cutting-edge server/storage OEMs and hyperscale data centers. Customers deploy DCS solutions into applications ranging from Big Data capacity storage to artificial intelligence and machine learning that are helping to shape the next digital age. Our product portfolio includes SAS/PCIe/NVMe/CXL products that connect, manage, and secure the world's information, including Flash Controllers, High Performance Switches, RAID Controllers and Memory Controllers. Join a team where you can expand your skill set and drive key elements of the industry's technology leadership.

Responsibilities

• Design of complex digital integrated circuits at the block, subsystem or device level (100K to 50M+ gates), which are coded in Verilog, System Verilog
• Define subsystem/block feature sets, describe design and implementation details into engineering documents and registers documents
• Support emulation, ASIC lab validation including lab debug and providing logic modifications and workarounds
• Communicate regularly with the design and verification team in multiple locations to resolve issues, communicate status and solve technical problems
• Communicate with architects to justify design implementation decisions and associated trade-offs
• Read and understand applicable storage and computer interface protocol standards

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or equivalent
• 10+ years related experience
• RTL Design - Experience in RTL Design using System Verilog, Verilog is required
• Experience and understanding of complex ASIC design flows, including block and chip level simulation and debug, logic synthesis, static timing analysis, layout and revision control
• Experience with Formal Verification a plus
• Working knowledge of design and verification tools such as Synopsys Design Compiler, Cadence Incisive, waveform viewers, and other similar tools
• Scripting and programming skills using csh, bash, perl, python, tcl, etc.
• Protocol knowledge and experience in PCI-Express will be an asset
• Knowledge of AHB/AXI bus protocols is desired
• Excellent knowledge in logic synthesis and static timing analysis
• Experience in designing the chip top level with IOs, pin out and package design
• Worked with physical design teams for layout implementation. Familiar with low power methodology and flows
• Capable of debugging EDA tool issues or design related issues
• Working knowledge of DFT
• Excellent analytical and debugging skills and the ability to proactively solve issues
• Good verbal and written communication skills in English will be an asset
• Excellent teamwork and time management skills, self-direction, the ability to work under pressure and the desire to excel in a competitive environment

Nice-to-haves

• Experience with Formal Verification
• Protocol knowledge and experience in PCI-Express
• Knowledge of AHB/AXI bus protocols

Benefits

• Competitive base pay
• Restricted stock units
• Quarterly bonus payments
• Health benefits that begin day one
• Retirement savings plans
• Industry leading ESPP program with a 2 year look back feature