Principal Signal & Power Integrity Engineer

Kforce - Phoenix, AZ

Full-time - Principal

Hybrid - Phoenix, AZ

Administrative and Support Services

About the position

The Principal Signal & Power Integrity Engineer will play a crucial role in collaborating with IC package design engineers to develop design solutions for high-speed and low-speed signals, power delivery signals, and power and ground planes. This hybrid position requires the candidate to work three days in the office and two days remotely, focusing on signal integrity analysis and optimization to meet specifications for semiconductor IC package design.

Responsibilities

• Work with IC package design engineers to provide design solutions for high-speed and low-speed signals, clocks, power delivery signals, and power and ground planes.
• Provide routing guidelines for high-speed, low-speed, power signals, power, and ground planes from bumps to balls.
• Collaborate with customers, package design engineers, simulation engineers, R&D, and assembly teams.
• Provide package layer counts, stack-ups, materials, impedance control, test impedance targets, and optimize net assignments for signals.
• Perform SIPI simulation/optimization to ensure signals meet required specifications.
• Conduct signal integrity analysis of frequency and time domain simulations for high-speed and low-speed signals following specifications.
• Optimize single-ended or differential Insertion loss, return loss, X-talk, & power sum X-talk for differential signaling groups and protocols.
• Perform IR_DROP simulation for the power rails from bumps to balls.
• Conduct AC frequency sweep simulation to optimize high RLC traces to achieve low resistance & inductance traces.
• Measure power plane resonance to assess the resonances of the package planes.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Physics, Computer Engineering or similar field.
• At least 4 to 8+ years of Signal and/or Power Integrity (SI/PI) Engineering experience or similar.
• Experience with package layout tools such as Cadence APD, SiP, or similar tools is a plus.
• Experience with high-speed bus design compliance such as DDR5, PCIe5, 56 GBPS and 112 GBPS PAM4 is ideal.
• Experience working with customers, global design & simulation teams and/or EDA tool vendors is a plus.
• Knowledge of next generation advanced high speed package design/simulation to meet electrical performance or similar is preferred.
• Strong background in the application of Electromagnetics and High-Speed Transmission Line principles related to signal and power integrity.
• Proficiency in time and frequency domain modeling and use of 2D and 3D simulation tools such as Ansys HFSS, SIwave, Cadence/Sigrity, ADS.
• Demonstrated effective verbal/written communication skills.
• Excellent analytical and problem-solving skills.
• Ability to perform as an individual contributor and team player.

Nice-to-haves

• Understanding of the SI and PI associated with bump signals/ground patterns and ability to optimize the balls signal/ground placement to improve performance.

Benefits

• Medical, dental, and vision insurance
• Health Savings Account (HSA)
• Flexible Spending Account (FSA)
• 401(k) retirement plan
• Life insurance
• Disability insurance
• Paid time off for salaried personnel