Principal SoC Design Engineer

ARM-posted about 1 year ago

$221,127 - $299,172/Yr

Full-time • Principal

Hybrid • San Diego, CA

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The Principal SoC Design Engineer will be part of the Solution Engineering division at ARM, focusing on the development of System on Chips (SoCs) for various applications. This role involves collaborating with a dedicated team to design, specify, and verify high-performance compute and AI solutions, utilizing the latest IP products from ARM and other vendors. The engineer will engage in all stages of the design process, from initial concept to implementation, while also mentoring team members and working closely with various internal groups to optimize performance and power.

Develop logic for high-performance compute and AI solutions as part of a design team.
Understand and review SoC architecture to create design specifications that meet power/performance goals.
Craft design micro-architecture specifications and develop RTL.
Fix bugs, run design checks, and contribute to implementation constraints generation.
Collaborate with the verification team to review test plans and debug design issues.
Work with performance/power analysis teams to evaluate and improve SoC performance/power.
Contribute to the development and enhancement of design methodologies used by the team.
Mentor and support other team members to ensure successful project completion.
Collaborate with Project Management on plans and schedules.

Bachelor's or Master's degree in Computer Science or Electrical/Computer Engineering or a related field.
10+ years of experience in the design of complex compute subsystems or SoCs.
Experience in digital hardware design for complex systems using Verilog HDL.
Experience with power and clock domain crossing and static design checks like linting, CDC/RDC, X-propagation.
Exposure to all stages of design: initial concept, specification, implementation, power and performance analysis, power optimization, testing, documentation, and support.
Experience or knowledge in synthesis, timing constraints, and power management techniques.
Experience collaborating with the verification team on design quality closure.
Experience with Perl, Python, or other scripting languages.
Leadership, mentoring, or coaching experience.

Experience with ARM-based designs and/or ARM System Architectures.
Experience with SystemVerilog and verification methodologies - UVM/OVM/e.
Experience with UPF, IP-XACT.
Experience leading teams or projects.
Experience developing and integrating subsystems for PCIe, UCIe, DDR/LPDDR/HBM, Ethernet, etc.
Understanding of DFT topics: RTL testability, scan insertion, OCC.

Competitive salary range of $221,127-$299,172 per year.
Hybrid working model that allows flexibility between office and remote work.
Support for accommodations during the recruitment process.
Commitment to equal opportunities and a diverse work environment.

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