Principle RTL Design Engineer

About the position

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You are a seasoned Logic Design Engineer with a passion for cutting-edge technology and a keen eye for detail. You thrive in a dynamic environment and are driven by the challenge of developing high-performance digital designs. With extensive experience in Serdes, or DDR/HBM, or Die to Die PHY logic, you excel at collaborating with cross-functional teams to deliver innovative solutions. Your expertise in PHY IP and SOC RTL design and verification, along with your ability to work independently with minimal oversight, makes you a valuable asset to any project. You possess a strong understanding of the full IP/SOC Design Cycle and have a proven track record of success in designing, developing, and evaluating physical IP such as SERDES, DDR and Die to Die Interconnect. Your excellent communication skills allow you to effectively convey complex technical concepts to both technical and non-technical audiences, and you are always eager to learn and adapt to new technologies and methodologies.

Responsibilities

• Designing and developing high-performance digital logic for the Synopsys' fast growing high-speed Die to Die interconnect IP portfolio
• Collaborating with cross-functional teams to define and implement best in class Die to Die IP design at PHY and controller levels
• Design and optimize Die to Die IP for best in class performance, power, and area
• Participating in the full Hard IP Design Cycle, including front-end and back-end design processes, post silicon support and customer support
• Conducting design reviews and providing technical guidance to junior engineers in highly matrixed global IP organization
• Staying up-to-date with industry trends and emerging technologies to continuously improve design methodologies

Requirements

• Extensive experience in Serdes, or DDR/HBM, or UCIe PHY architecture and logic implementation
• Expertise in design of Hard IP such as SERDES or DDR/HBM or Die to Die IO interconnect
• Proficiency in SystemVerilog design and verification at SOC, IP and behavioral modeling at analog building block level
• Proficiency in end to end RTL to gate level design flow and methodology such as FEV, UPF, CDC, timing and ECO etc
• Strong understanding of the full IP/SOC Design Cycle
• Excellent problem-solving skills and attention to detail
• Experience in leading and driving technical solutions across organization
• Good written & verbal communication skills and ability to work in cross functional and globally dispersed teams

Benefits

• Comprehensive health, wellness, and financial benefits
• Annual bonus eligibility
• Equity and other discretionary bonuses
• Competitive total rewards package