Product Engineering Manager, Digital Mixed-Signal

$121,400 - $218,500/Yr

Siemens - Austin, TX

Part-time,Full-time - Mid Level

Remote - Austin, TX

10,001+ employees

Machinery Manufacturing

About the position

We are seeking an experienced Senior Digital/Mixed-Signal Product Engineering Manager to join our team at Siemens Industry Software Inc. In this critical role, you will define product strategies, refine verification methodologies, and collaborate with various teams to drive innovation and productivity in design verification. This position is pivotal in ensuring that our products meet the highest standards of quality and functionality, and it requires a deep understanding of both technical and managerial aspects of product engineering. As a Product Engineering Manager, you will be responsible for defining product strategy and contributing to product definition by collaborating with Design Verification engineers to invent new use models, features, or products. You will develop and refine verification methodologies related to Analog modeling and RTL design verification, addressing functional verification challenges and enhancing design verification productivity. Your role will also involve collaborating with customers and stakeholders, including regional application engineers, global support engineers, and marketing teams, to ensure alignment and drive product success. In addition to external collaboration, you will work closely with internal R&D teams on new Questasim features within complex IC design and verification flows. You will drive product adoption through strategic initiatives and effective communication, and you will be responsible for building and delivering technical presentations, white papers, contributed articles, and application notes to share knowledge and promote best practices. Continuous improvement is key, and you will complete enhancement and defect reports to address product gaps and defects, ensuring that our products evolve to meet user needs. Finally, you will develop test cases for quality assurance based on real-world user scenarios to maintain product quality.

Responsibilities

• Define product strategy and contribute to product definition by collaborating with Design Verification engineers.
• Develop and refine verification methodologies related to Analog modeling and RTL design verification.
• Address functional verification challenges and enhance design verification productivity.
• Collaborate with customers and stakeholders to ensure alignment and drive product success.
• Work closely with internal R&D teams on new Questasim features within complex IC design and verification flows.
• Drive product adoption through strategic initiatives and effective communication.
• Build and deliver technical presentations, white papers, contributed articles, and application notes.
• Complete enhancement and defect reports to address product gaps and defects.
• Develop test cases for quality assurance based on real-world user scenarios.

Requirements

• Bachelor's or master's degree in computer science, Electrical Engineering, or a related field.
• Minimum of 12 years of experience in RTL design and verification for FPGAs/ASICs.
• Strong proficiency in design languages, including Verilog, Verilog-A, Spice, and SystemVerilog.
• Familiarity with simulators like QuestaSIM, Xcelium, and VCS.
• Expertise in RTL coding and verification using Verilog, SystemVerilog, VHDL, or C & SystemC.
• In-depth knowledge of Real Number Modeling (RNM).
• Strong problem-solving and analytical skills to address complex design verification challenges.
• Excellent communication and presentation skills to effectively convey technical information to diverse audiences.

Benefits

• Health and wellness benefits
• Paid sick leave
• Paid parental leave
• PTO (for non-exempt employees)
• Non-accrued flexible vacation (for exempt employees)