Google - San Diego, CA
posted 4 months ago
As a member of our diverse team at Google, you will play a crucial role in developing custom silicon solutions that power the future of our direct-to-consumer products. Your contributions will be integral to the innovation behind products that are loved by millions worldwide. In this position, you will be responsible for the RTL design development of camera and machine learning designs. This encompasses a variety of tasks including RTL coding, lint cleanup, SoC IP release flows, architecture, micro-architecture, and optimizations for power, performance, and area (PPA). You will also engage in test planning collaboration, coverage reviews, and closure to ensure high-quality and optimized Core IP deliveries. Your expertise will help shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. You will be part of a team that combines the best of Google AI, Software, and Hardware to create radically helpful experiences. Our mission is to organize the world's information and make it universally accessible and useful, and your work will contribute to making computing faster, seamless, and more powerful, ultimately improving people's lives through technology. In this role, you will perform Verilog/SystemVerilog RTL coding, function/performance simulation debugging, and Lint/CDC/FV/UPF checks. You will also be involved in RTL verification using industry-standard methodologies, participate in test planning and coverage analysis, and develop RTL implementations that meet engaged power, performance, and area goals. Additionally, you will participate in synthesis, timing/power closure, and FPGA/silicon bring-up, as well as create tools/scripts to automate tasks and track progress.