RTL Design Engineer - Memory Controller

ARM - Austin, TX

Full-time - Mid Level

Austin, TX

About the position

As an RTL Design Engineer at ARM, you will play a crucial role in the development of the Memory Controller, which is a key component in high-performance and power-efficient systems. Your responsibilities will include working closely with performance modeling, validation, and implementation teams to ensure that all functional requirements and performance, power, and area (PPA) goals are met. You will be involved in the development of high-level specifications and requirements for Memory Controller products, as well as defining detailed micro-architecture plans. Your primary focus will be on the development and implementation of SystemVerilog RTL logic design for sophisticated blocks and functions within the design. Collaboration is essential in this role, as you will work with key partners on the design and verification teams to close on functional and coverage requirements. Additionally, you will be responsible for debugging functional and/or performance issues within the RTL using modern simulation and debug tools. This position requires a strong understanding of DRAM specifications and bus protocols, as well as experience in RTL design and synthesis.

Responsibilities

• Develop high-level specifications and requirements for Memory Controller products.
• Define detailed micro-architecture plans.
• Develop and implement SystemVerilog RTL logic design for sophisticated blocks and functions within the design.
• Collaborate with design and verification teams to close on functional and coverage requirements.
• Debug functional and/or performance issues within the RTL using modern simulation and debug tools.

Requirements

• Bachelor's or Master's degree in Computer Science or Electrical/Computer Engineering.
• Prior RTL design experience is required.
• 5+ years work experience in microprocessor, SoC, memory controller and/or interconnect IP design.
• Knowledge of DRAM specification (e.g., LPDDR4/5, DDR4/5) and of bus protocols (e.g., AMBA5 CHI, AMBA4 ACE or AXI).
• Experience with Verilog or VHDL, coupled with design synthesis targeted to achieve specified frequency, power, and area targets.

Nice-to-haves

• Prior verification or CAD experience is a plus.
• Experience with CPU or compute subsystem memory micro-architecture.
• Processor system knowledge including basic understanding of SoC systems as well as operating system software.

Benefits

• Hybrid approach to home and office working to provide an adaptable experience for all employees.