RTL Design Engineer

Apple - Austin, TX

Full-time - Senior

Austin, TX

Computer and Electronic Product Manufacturing

About the position

As an RTL Design Engineer at Apple, you will be part of a dynamic team dedicated to crafting innovative products that enhance the lives of millions. This role presents a unique opportunity to engage in the specification, design, and verification of advanced mixed-signal circuits, particularly focusing on the digital aspects. You will be responsible for micro-architecting digital blocks, which involves not only the design but also the RTL coding of these blocks, whether they are specified by you or others in the team. Your contributions will be crucial in the design verification process, where you will write meaningful assertions, debug code, and collaborate closely with the design verification team to ensure the highest quality of the digital blocks you create. In addition to design and verification, you will also play a key role in the lab bring-up of these circuits. This may involve writing test scripts, analyzing lab data, and proposing experiments to validate the functionality of the circuits. Your work will directly impact the development of products that are at the forefront of technology, and you will have the chance to solve complex challenges that have not been addressed before. This position is ideal for someone who is forward-thinking, hardworking, and passionate about making a difference in the tech industry.

Responsibilities

• Specify and/or micro-architect digital blocks in advanced mixed-signal circuits.
• Perform RTL coding of blocks specified by yourself or others.
• Participate in design verification by writing meaningful assertions and debugging code.
• Collaborate with the design verification team to ensure quality and functionality of designs.
• Engage in lab bring-up of circuits by writing test scripts and analyzing lab data.
• Propose experiments to validate circuit functionality.

Requirements

• Deep knowledge of mixed signal concepts.
• Deep knowledge of RTL design fundamentals.
• Deep knowledge of Verilog and System-Verilog.
• Deep knowledge of front-end tools such as Verilog simulators, linters, and clock-domain crossing checkers.
• Working knowledge of synthesis, static timing, and DFT is a huge plus.
• Deep knowledge of System-Verilog assertions, checkers, and other design verification techniques.
• Deep knowledge of scripting languages, with Perl and Python as plusses.
• Deep knowledge of algorithm developments.
• Strong communication and presentation skills.
• Knowledge of SERDES is a plus.