Senior Analog IC Design Engineer

$130,000 - $165,000/Yr

Eridan - Sunnyvale, CA

Full-time - Senior

Sunnyvale, CA

Computer and Electronic Product Manufacturing

About the position

Eridan is looking for an experienced and detail-oriented Senior Analog IC Design Engineer to join our dynamic team. In this role, you will be involved in the full CMOS design life cycle, from design and simulation to layout, quality checks, and tapeout. You will work on various tasks requiring expertise in data converter and analog building block design, clocking systems, and more. If you are passionate about CMOS design and have experience in analog systems and tapeouts, we invite you to apply.

Responsibilities

• Participate in the full CMOS design process, including design, simulation, layout, quality checks, and tapeout tasks.
• Work on the design of analog building blocks and data converters, ensuring they meet specifications and quality standards.
• Understand and apply clocking principles to the designs.
• Contribute to the layout design and ensure it meets process and quality requirements.
• Contribute to successful tapeouts by ensuring designs meet all necessary requirements and quality checks.
• Use Cadence tools for simulation, design, and layout tasks, ensuring efficiency and accuracy.
• Support integration of analog designs with system-on-chip (SOC) components, including voltage references, I/O circuits, and flip-chip/package design flow.
• Apply knowledge of pad planning and electrostatic discharge (ESD) protection to designs.
• Collaborate with fellow team members on continuous improvement opportunities in the flow, layout techniques, and design methodologies.

Requirements

• A PhD in electrical engineering with 5 years of experience, an MS with 7 years, or a BS with 10 years of experience.
• Experience with CMOS custom design, including design, simulation, layout, and tapeout processes.
• Expertise in analog design principles.
• Experience using Cadence tools for IC design and layout.
• Knowledge of clocking systems and analog layout principles.
• Proven success in completing tapeouts and meeting design specifications.
• Understanding of process corners and their impact on design performance.
• Experience in chip bring up and debug.

Nice-to-haves

• Experience with DLL and PLL design.
• Background in system and SOC integration, including voltage references, I/O circuits, and flip-chip/package design flow.
• Familiarity with ESD protection techniques and pad planning.
• Knowledge of digital and mixed-signal design.
• Experience with receiver design.
• Experience with data converters design.

Benefits

• Work on new technology that will make a significant impact on global infrastructure
• Ability to learn, develop, and advance within a flexible environment
• Collaborate with smart, passionate, and helpful co-workers
• Celebrate progress company-wide
• Pre-IPO equity
• 401K with automatic match
• Health, Vision and Dental insurance