Senior Design for Debug Architect and Methodology Engineer

$164,000 - $258,750/Yr

Nvidia - Santa Clara, CA

Full-time - Senior

Santa Clara, CA

Computer and Electronic Product Manufacturing

About the position

NVIDIA is seeking a Senior Design for Debug (DFD) Architect and Methodology Engineer to implement hardware and software solutions for debugging the world's leading System on Chips (SoCs) and Graphics Processing Units (GPUs). This position offers a unique opportunity to make a significant impact within a multifaceted, technology-focused company that spans product lines from consumer graphics to self-driving cars and the rapidly growing field of artificial intelligence. As a member of the GPU DFD team, you will be at the forefront of architecting and implementing silicon debug capabilities and infrastructure for our GPUs. In this role, you will identify debug inefficiencies and deficiencies, driving the exploration of silicon debug features. You will specify the architecture and track execution by collaborating with various teams across NVIDIA, including software, architecture, design, verification, and silicon validation teams. Additionally, you will have the responsibility of training and mentoring junior engineers and the team in silicon debug methodologies. Your expertise will be crucial in reviewing new features from a DFD perspective to enhance GPU debuggability and in verifying DFD hardware at the full-chip level. This position is ideal for someone who thrives in a dynamic environment and is eager to tackle complex challenges. You will be part of a team that continuously evolves by adapting to new opportunities and finding creative solutions to difficult problems, making a real impact in the technology landscape.

Responsibilities

• Architect and implement silicon debug capabilities and infrastructure for GPUs.
• Identify debug inefficiencies and deficiencies in current systems.
• Drive exploration of silicon debug features and specify the architecture.
• Collaborate with software, architecture, design, verification, and silicon validation teams.
• Train and mentor junior engineers in silicon debug methodologies.
• Review new features from a DFD perspective to improve GPU debuggability.
• Help verify DFD hardware at the full-chip level.

Requirements

• Bachelor's Degree or equivalent experience in Electrical Engineering, Computer Engineering, or Computer Science.
• 8+ years of meaningful work experience in relevant fields.
• Experience in Computer Architecture and RTL development (Verilog), focusing on arbiters, scheduling, synchronization & bus protocols, interconnect networks, and/or caches.
• Expertise in design for debug techniques and methodologies, integrated logic analyzers, and/or other silicon visibility tools.
• Strong understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis, and bringup.
• Strong interpersonal skills and ability to work effectively in a team.

Nice-to-haves

• Strong skills in C/C++, Python, Typescript, or Javascript.
• Good debugging and analytical skills.

Benefits

• Equity options as part of compensation package.
• Comprehensive health benefits including medical, dental, and vision insurance.
• 401(k) retirement savings plan with company matching contributions.
• Paid time off and holidays.
• Opportunities for professional development and training.