Senior DFT Engineer

Valtix - San Jose, CA

Full-time - Mid Level

San Jose, CA

Publishing Industries

About the position

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

Responsibilities

• Responsible for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug and diagnostics needs of the design.
• Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
• Work with the team on Innovative Hardware DFT & test strategy aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug methodologies and standards.
• Work with the team on DFT challenge identification, cross-functional solution brainstorming and implementation plan development, and lead junior engineers to deliver expected implementations on schedules.

Requirements

• Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 8 years of experience.
• Prior experience with the latest innovative trends in DFT, test and silicon engineering.
• Prior experience with scripting languages, Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
• Prior experience with hardware design specifications and verification plan/matrix, RTL & testbench implementations.
• Prior experience on DFT quality sign off checklist and reviews for chip tape out, including test coverage, STA.
• Prior experience with pre-silicon DFT implementation and verification flows, and post-silicon test bring up procedures.

Nice-to-haves

• DFT CAD development - Test Architecture, Methodology and Infrastructure.
• Post silicon validation using DFT patterns.

Benefits

• Quality medical, dental and vision insurance.
• 401(k) plan with a Cisco matching contribution.
• Short and long-term disability coverage.
• Basic life insurance.
• Numerous wellbeing offerings.
• Up to twelve paid holidays per calendar year.
• Flexible Vacation Time Off policy.
• Sick Time Off policy with 80 hours provided on hire date.
• Paid time away to deal with critical or emergency issues.
• Additional paid time to volunteer and give back to the community.