Senior Digital Integration & Timing Engineer

$166,600 - $296,300/Yr

Apple - Irvine, CA

Full-time - Senior

Irvine, CA

Computer and Electronic Product Manufacturing

About the position

Come and join Apple's growing wireless silicon development team. Our Wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and new technologies that transform the user experience at the product level. This is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. We encourage you to apply if you enjoy a fast-paced and exciting environment, collaborating with people across different functional areas, and thrive during critical times. As a Digital Integration & Timing Engineer, you will work in a team developing Wireless SoCs with custom hardware accelerators and multiple ARM-based sub-systems. You will have the opportunity to work closely with SoC architects and IP developers to develop SoCs that meet Apple devices' power, performance, and area goals. You will help define the processes, methods, and tools for designing and implementing these large, complex SoCs. Collaboration with multi-disciplinary groups will be needed to make sure designs are delivered on time and with the highest quality by incorporating accurate checks at every stage of the design process. In this highly visible role, you will be at the center of the ASIC creation effort, interfacing with all disciplines, with a critical impact on getting leading-edge products out to delight millions of customers.

Responsibilities

• Full chip and block-level timing constraint and closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation).
• Deploy and enhance methodology and flows related to timing constraint verification and timing closure.
• Generation of consistent block and full chip timing constraints.
• Support digital chip integration work and flows.
• Execute low power design and physical synthesis techniques, deploying knowledge of UPF and power intent verification.
• Collaborate with Chip Architecture, Design Verification, Physical Design, DFT, and power teams to achieve the tape out success on designs.

Requirements

• BS and 10+ years of relevant industry experience.
• Knowledge of the entire ASIC design flow from RTL integration through synthesis, static timing analysis, scripting, P&R to tapeout.
• Expertise in STA tools and flow.
• UPF usage for power and voltage islands.
• Hands-on experience in timing/SDC constraints generation and management.
• Knowledge of timing corners, operating modes, process variations, and signal integrity-related issues.
• Proficient in scripting languages (TCL and PERL).
• Logic synthesis execution for efficient PPA using physically aware techniques in single-digit process nodes using Design Compiler, Fusion Compiler &/or Genus.
• Proficient in the closure of end-to-end logic equivalence (FV, LEC) with functional ECOs in the mix.
• Familiarity with DFT and backend related methodologies and tools.
• Proficient with RTL Verilog/VHDL.
• Knowledge of digital top integration flows/methodology/checks.
• Experience with script-based tool automation, API's and scripting languages for EDA tools, such as; Design Compiler, Genus, PrimeTime, etc.

Nice-to-haves

• MSEE and PhD is preferred.

Benefits

• Comprehensive medical and dental coverage
• Retirement benefits
• A range of discounted products and free services
• Reimbursement for certain educational expenses - including tuition
• Discretionary bonuses or commission payments
• Relocation assistance
• Participation in Apple's discretionary employee stock programs
• Opportunity to purchase Apple stock at a discount through Employee Stock Purchase Plan.