Leidos - Arlington, VA

posted 3 months ago

Full-time - Senior
Arlington, VA
10,001+ employees
Professional, Scientific, and Technical Services

About the position

The EW Division of Leidos is seeking a Senior Microelectronics Design Engineer to join a multi-disciplined design team that includes electrical engineers, systems engineers, and scientists. This role is pivotal in designing, developing, simulating, and integrating innovative custom microelectronics to support warfighter missions. The ideal candidate will possess a robust background in Digital Signal Processing (DSP) algorithms and their implementation using MATLAB and FPGAs, contributing to a fast-paced, multi-disciplinary design environment. The position also involves supporting integration, testing, and verification of final products, ensuring that they meet the required specifications and performance standards. In this role, the successful candidate will be responsible for conducting technical and programmatic assessments of various technologies, capabilities, materials, equipment, and performers. This is essential for advancing the U.S. Defense Industrial Base's access to trusted, state-of-the-art microelectronics. The engineer will lead or support marketing and business development initiatives, developing technical solutions and innovative ideas in response to capture efforts such as Broad Agency Announcements (BAAs) and Requests for Proposals (RFPs). The Senior Microelectronics Design Engineer will lead a design team focused on creating, integrating, and testing complex DSP FPGA designs for Electronic Warfare (EW) sensor systems. This position requires collaboration with a diverse range of professionals, including engineers, scientists, policymakers, and executives across government, industry, and academia. The engineer will also provide occasional technical support and field support planning, conducting experimental tests on the latest System on Chip (SoC) evaluation boards, evaluating results, and developing specifications for selecting next-generation components for deliverable systems. Interaction with customers, suppliers, and functional peer groups is also a key aspect of this role, along with the need for occasional travel to remote sites for limited periods.

Responsibilities

  • Support technical and programmatic assessments of technologies, capabilities, materials, equipment, and performers.
  • Lead or support marketing and business development initiatives, developing technical solutions and new ideas for capture efforts.
  • Lead a microelectronics design team to design, integrate, and test DSP FPGA designs for EW sensor systems.
  • Interface and collaborate with engineers, scientists, policymakers, and executives across government, industry, and academia.
  • Provide technical support and field support planning as needed.
  • Conduct experimental tests on SoC evaluation boards and evaluate results to develop specifications for next-generation components.
  • Interact with outside customers, suppliers, and functional peer groups.
  • Communicate results in briefings and written materials to the team, customers, and management.

Requirements

  • U.S. Citizenship with a Secret-level clearance and ability to obtain a TS clearance.
  • Bachelor's degree with 12 years of experience; Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 6+ years of experience is preferred.
  • Experience with DSP fundamentals and FPGA implementation.
  • Proficiency in MATLAB/Simulink.
  • Experience with microchip EDA tools and flows (e.g., Synopsys, Cadence).
  • Subject matter expertise in at least one area of microelectronics hardware and experience in one additional area.

Nice-to-haves

  • 8+ years of experience in leading a design team.
  • Experience in hardware test and measurement and hands-on lab debugging.
  • Familiarity with interfaces such as ADC/DACs, SerDes, PCIe, JTAG, DDRx.

Benefits

  • Competitive compensation
  • Health and wellness programs
  • Life protection
  • Paid leave
  • Retirement plans
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