Senior Package Layout Engineer - Hardware

$128,000 - $247,250/Yr

Nvidia - Santa Clara, CA

Full-time - Senior

Santa Clara, CA

Computer and Electronic Product Manufacturing

About the position

NVIDIA's GPUs and SOCs are the world leaders in power, performance, and efficiency. We are continually innovating to deliver new and creative, unusual solutions to extraordinary problems in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Package Layout Engineer who is committed to making a difference in the world through their contributions! This position will collaborate with the Technical Package Lead and different design teams in the design and development of complex, detailed layout of IC substrates for NVIDIA products. In addition, work with design teams to plan schedules, resolve costs, manufacturing, and electrical design issues. As part of a Layout team, you will collaborate to implement high speed/density ASIC packages. You will perform substrate breakout patterns for ASIC packages and optimize package pinout incorporating system level trade-offs of pins assignment. You will help perform package routing, placement, stack-up, reference plane, and power distribution using Cadence APD or SiP tool suite. You will propose layout design trade-offs to the Technical Package Lead for resolution and implementation. Additionally, you will conduct design feasibility studies to evaluate the Package design goals for size, cost, and system performance. You will also develop symbols and CAD library databases using Cadence APD design tools and develop methodologies to improve layout productivity.

Responsibilities

• Collaborate with Technical Package Lead and design teams in the design and development of IC substrates.
• Implement high speed/density ASIC packages as part of the Layout team.
• Perform substrate breakout patterns for ASIC packages.
• Optimize package pinout incorporating system level trade-offs of pins assignment.
• Help perform package routing, placement, stack-up, reference plane, and power distribution using Cadence APD or SiP tool suite.
• Propose layout design trade-offs to the Technical Package Lead for resolution and implementation.
• Conduct design feasibility studies to evaluate the Package design goals for size, cost, and system performance.
• Develop symbols and CAD library databases using Cadence APD design tools.
• Develop methodologies to improve layout productivity.

Requirements

• Hold a B.S. in Electrical Engineering or equivalent experience.
• 5+ years experience in PCB Layout of graphics cards, motherboards, line cards or other related technology.
• Experience with HDI designs is a plus.
• Proven experience in substrate layout of wire bond and flip chip packages, preferred.
• Significant background with Cadence APD or SiP and/or PCB layout tools (including Constraint Manager).
• Validated working knowledge of high-speed design signal integrity practices.
• Experience using Valor is helpful.

Benefits

• Equity and benefits eligibility based on location and experience.