Senior Physical Design Engineer, Hardware Compute Group

$143,300 - $247,600/Yr

Amazon - Sunnyvale, CA

Full-time - Senior

Sunnyvale, CA

Sporting Goods, Hobby, Musical Instrument, Book, and Miscellaneous Retailers

About the position

The Senior Physical Design Engineer will be part of the Hardware Compute Group at Amazon Lab126, focusing on the physical design of innovative silicon IP for the latest generation of Echo devices. This role involves collaborating with RTL/logic designers to ensure architectural feasibility, driving physical implementation processes, and working closely with third-party design and fabrication services to achieve high-quality silicon outcomes. The engineer will also contribute to the development of physical design methodologies and work within a collaborative team environment.

Responsibilities

• Work with RTL/logic designers to drive architectural feasibility studies and explore power-performance-area tradeoffs for physical design closure.
• Drive block physical implementation through various processes including synthesis, formal verification, floor planning, and place and route.
• Collaborate with third-party design and fabrication services to deliver quality first pass silicon that meets performance, power, and area goals.
• Contribute to developing physical design methodologies.
• Collaborate effectively with other physical design engineers and RTL/Arch teams.

Requirements

• BS in Electrical Engineering or Computer Science.
• 7+ years of experience in ASIC Physical Design from RTL-to-GDSII in FINFET technologies such as 5nm/7nm, 14/16nm.
• Expertise using CAD tools (e.g., Cadence, Mentor Graphics, Synopsys) for various physical design tasks.
• Scripting experience with Tcl, Perl, or Python for physical design flow automation.

Nice-to-haves

• MS or PhD degree in Computer Engineering/Electrical Engineering or related field.
• Excellent communication and analytical skills.
• Experience in integrating IP and specifying IP requirements in the physical domain.
• Thorough knowledge of device physics and custom/semi-custom implementation techniques.
• Experience solving physical design challenges across various technologies such as CPU, DDR, PCIe.
• Experience with DFT & DFM flows.
• Ability to mentor and guide junior engineers.

Benefits

• Medical, dental, and vision insurance
• 401(k) retirement plan
• Paid time off and holidays
• Employee discounts
• Equity and sign-on payments as part of total compensation package