Amazon - Sunnyvale, CA

posted about 1 month ago

Full-time - Senior
Sunnyvale, CA
Sporting Goods, Hobby, Musical Instrument, Book, and Miscellaneous Retailers

About the position

The Senior Physical Design Engineer will be a key member of the team responsible for advancing the physical design of innovative silicon IP for Amazon's hardware products, including the latest generation of Echo devices. This role involves collaborating with RTL/logic designers to optimize power-performance-area tradeoffs and ensuring high-quality silicon delivery through effective physical design methodologies and teamwork.

Responsibilities

  • Work with RTL/logic designers to drive architectural feasibility studies and explore power-performance-area tradeoffs for physical design closure at the block and subsystem level.
  • Drive block physical implementation through synthesis, formal verification, floor planning, bus/pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO, and sign-off.
  • Collaborate closely with third-party design and fabrication services to deliver quality first-pass silicon that meets all performance, power, and area goals.
  • Contribute to developing physical design methodologies.
  • Collaborate effectively with other physical design engineers and RTL/Arch teams.

Requirements

  • BS in Electrical Engineering or Computer Science.
  • 7+ years of experience in ASIC Physical Design from RTL-to-GDSII in FINFET technologies such as 5nm/7nm, 14/16nm.
  • Expertise using CAD tools (e.g., Cadence, Mentor Graphics, Synopsys) for various physical design tasks.
  • Scripting experience with Tcl, Perl, or Python to drive physical design flow automation.

Nice-to-haves

  • MS or PhD degree in Computer Engineering/Electrical Engineering or related field.
  • Excellent communication and analytical skills.
  • Experience in integrating IP and specifying IP requirements in the physical domain.
  • Thorough knowledge of device physics and custom/semi-custom implementation techniques.
  • Experience solving physical design challenges across various technologies such as CPU, DDR, PCIe, fabrics, etc.
  • Experience with DFT & DFM flows.
  • Ability to provide mentorship and guidance to junior engineers.

Benefits

  • Competitive salary based on market location and experience.
  • Equity and sign-on payments as part of total compensation package.
  • Comprehensive medical, financial, and other benefits.
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