Senior Quantum Digital Application-Specific Integrated Circuit (ASIC) Design Engineer

$117,200 - $229,200/Yr

Microsoft - Redmond, WA

Full-time - Senior

Redmond, WA

Publishing Industries

About the position

Microsoft Quantum has assembled a talented and diverse international team to create the world's first scalable quantum computing system. Our full-stack approach involves exciting innovations from physics on the quantum plane to providing global quantum services. The Microsoft Quantum program strives to fundamentally change the world of computing to help solve humankind's currently unsolvable problems. We are on the cusp of an accelerated effort in quantum computing. This position offers an opportunity to have a meaningful influence on a revolutionary technology. The research effort includes a diverse staff of theoretical and experimental physicists, hardware designers, and software engineers around the world. Our Cryogenic Complementary Metal-Oxide Semiconductor (CryoCMOS) team is looking for a Senior Quantum Digital Application-Specific Integrated Circuit (ASIC) Design Engineer to work as a digital ASIC designer to participate in the research and development of essential building blocks in the control and readout chain of our quantum hardware implementations. This role involves deep, technical work in a small, collaborative environment. We are looking for a Senior Quantum Digital Application-Specific Integrated Circuit (ASIC) Design Engineer who is as passionate about their own contribution as they are to empowering and inspiring others. The Senior Quantum Digital Application-Specific Integrated Circuit (ASIC) Design Engineer will be responsible for contributing to the technical direction of the research based on system and block design ideas and simulations, experimental results, program needs, and the input from cross-functional colleagues. Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees, we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day.

Responsibilities

• Contribute to the architecture, specification, design, test, and development of CryoCMOS functions and ASICs to support the full-stack quantum hardware implementations.
• Be responsible for Logic design/Register Transfer Level (RTL) entry.
• RTL to GDS implementation in Physical Design domain, from synthesis to place and route of partitions through all signoffs including timing signoff, physical verification, EMIR signoff, and Low Power Verification.
• Define and implement efficient UVM-based verification environments and use them to verify and test digital designs.
• Create test plans, tests, and infrastructure to complete functional validation of complex designs and report bugs/issues.
• Work closely with the analog, architecture, and cryogenics teams to optimize tradeoffs within the design.
• Conduct cryogenic and room temperature measurements of the ASICs and perform analysis and reporting of the measurement results.
• Use lab best practices and protocols.
• Work in accordance with health and safety policies and take care that your actions do not impact the health and safety of yourself or others.
• Ensure hazards and risks are identified and controlled for within your area of responsibility.

Requirements

• Bachelor's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment OR Master's Degree in Physics, Engineering, or related field AND 4+ years experience in industry or in a research and development environment OR Doctorate in Physics, Engineering, or related field AND 1+ year(s) experience in industry or in a research and development environment, could include completion of a post-doctoral research position OR equivalent experience.
• 4+ years of experience in digital logic design including microarchitecture specification development, RTL coding in Verilog/System Verilog, design verification collaboration, and CDC/Lint closure.
• 4+ years of experience in synthesis, floorplanning, timing constraints, power/performance/area (PPA) trade-offs, and post-silicon debug.

Nice-to-haves

• 10+ years of industry experience in logic design delivering complex solutions.
• Successful Application-Specific Integrated Circuit (ASIC) tape outs in deep sub-micron technologies.
• Good background in debugging designs as well as simulation environment.
• Knowledge of verification principles, testbenches, Universal Verification Methodology (UVM), and coverage.
• Deep experience with EDA software for digital design (Cadence suite).
• Experience/exposure to low-temperature circuit design and measurements is desirable.
• Knowledge of quantum physics, behavior of semiconductors at cryogenic temperatures is desirable.

Benefits

• Health insurance coverage
• Dental insurance coverage
• Vision insurance coverage
• 401(k) retirement savings plan
• 401(k) matching contributions
• Paid holidays
• Paid time off (PTO)
• Flexible scheduling options
• Professional development opportunities
• Tuition reimbursement
• Employee stock purchase plan
• Life insurance coverage
• Disability insurance coverage
• Mental health days
• Wellness programs