Synopsys - Sunnyvale, CA

posted 2 months ago

Full-time - Senior
Sunnyvale, CA
Publishing Industries

About the position

Synopsys is seeking a Senior R&D Engineer to join our Logic Library Group in Sunnyvale, CA. This role is pivotal for the design and development of standard cell libraries, which are essential components in integrated circuit design. The ideal candidate will possess a strong background in standard cell library design, with a minimum of 7 years of experience in this field. The position requires a hands-on approach to development, as well as the ability to mentor and coach junior engineers, fostering their growth and skill expansion. The successful candidate will work closely with geographically distributed R&D teams, engaging in cross-functional collaborations to optimize the design chain. Effective communication skills are crucial, as the role involves articulating ideas and requests to drive these collaborations. The candidate must have experience with advanced technology nodes, specifically 7nm, 6nm, 5nm, 4nm, and 3nm, and should be adept in circuit design, layout design, and spice simulations. A deep understanding of CMOS device characteristics and design rules in submicron process nodes is essential, along with knowledge of submicron process issues, particularly in FINFET technologies. The candidate should be familiar with high sigma variation analysis in smaller technology nodes and have experience in optimizing standard cell circuits to achieve better performance, power, and area (PPA). Collaboration with layout designers to optimize layout parasitics and involvement in layout extraction are also key aspects of this role. Additionally, the candidate should possess scripting capabilities in TCL, PERL, or Python, and demonstrate strong analytical and logical skills. At Synopsys, we are at the forefront of innovations that transform the way we work and live, contributing to advancements in self-driving cars, artificial intelligence, cloud computing, 5G, and the Internet of Things. Our Silicon IP business focuses on integrating more capabilities into System on Chips (SoCs) at a faster pace, offering a broad portfolio of silicon IP to help customers meet their unique performance, power, and size requirements. We are committed to inclusion and diversity, considering all applicants without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Responsibilities

  • Design and develop standard cell libraries for advanced technology nodes.
  • Mentor and coach junior R&D engineers to enhance their skills.
  • Collaborate with geographically distributed R&D teams for optimization across the design chain.
  • Articulate ideas and requests effectively to drive cross-functional collaborations.
  • Conduct circuit design, layout design, and spice simulations.
  • Design complex circuits including flip-flops, clock gating cells, level shifters, and power gating cells.
  • Understand and apply CMOS device characteristics and design rules in submicron process nodes.
  • Analyze submicron process issues, particularly in FINFET technologies.
  • Run high sigma variation analysis in smaller technology nodes.
  • Optimize standard cell circuits to achieve better performance, power, and area (PPA).
  • Work with layout designers to optimize layout parasitics and achieve target PPA.
  • Involve in layout extraction and understand layout dependent parameters in the extracted netlist.
  • Characterize timing and leakage of standard cells.
  • Utilize scripting skills in TCL, PERL, or Python for automation and analysis.

Requirements

  • Bachelor's or MSEE or equivalent from reputed universities.
  • 7+ years of experience in standard cell library design.
  • Hands-on development experience in circuit and layout design.
  • Ability to mentor and coach junior engineers.
  • Experience working with advanced technology nodes (7nm, 6nm, 5nm, 4nm, 3nm).
  • Strong understanding of CMOS device characteristics and design rules in submicron process nodes.
  • Knowledge of submicron process issues, especially in FINFET technologies.
  • Experience in high sigma variation analysis in smaller technology nodes.
  • Proficiency in optimizing standard cell circuits for better PPA.
  • Familiarity with layout design and working with layout designers.
  • Experience in layout extraction and understanding of layout dependent parameters.
  • Strong scripting skills in TCL, PERL, or Python.
  • Excellent analytical and logical skills.

Nice-to-haves

  • Experience with machine learning applications in circuit design.
  • Familiarity with EDA tools and methodologies.
  • Knowledge of power integrity and signal integrity analysis.

Benefits

  • Comprehensive health insurance coverage.
  • Wellness programs and resources.
  • 401(k) retirement savings plan.
  • Annual bonus and equity options.
  • Discretionary bonuses based on performance.
  • Flexible working hours and remote work options.
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