Senior Test and Integration Engineer

$122,200 - $220,900/Yr

Leidos - Linthicum Heights, MD

Full-time - Senior

Linthicum Heights, MD

Professional, Scientific, and Technical Services

About the position

Leidos is currently seeking a Senior Test and Integration Engineer to join a Cyber Security Program located near Ft. Meade, MD. This position is critical to the success of a complex, mission-critical program, where the successful candidate will be responsible for the installation, integration, and testing of operational equipment and software. The primary goal is to ensure compliance with system design, requirements, and standards. The role involves performing in-depth security verification testing of cryptographic product designs and equipment, which is essential for maintaining the integrity and security of the systems involved. In this role, the engineer will prepare interactive Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) test benches and write test scripts using programming languages such as "C" and "Tcl/TK". The engineer will conduct functional verification and testing of new ASIC designs prior to fabrication, utilizing Field Programmable Gate Arrays (FPGA) to emulate the chips. Additionally, the engineer will be responsible for writing custom interfaces between Commercial off the Shelf (COTS) software and Mentor Graphics products, employing advanced verification methodologies using the industry-standard Unified Verification Methodology (UVM). The position also requires performing functional testing on variants, prototype devices, and production versions of ASIC chip designs following production. The engineer will design in-depth security verification tests to ensure that all systems meet the necessary security standards and protocols. This role is pivotal in ensuring that the systems are not only functional but also secure against potential threats, making it a challenging yet rewarding position for the right candidate.

Responsibilities

• Prepare interactive Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) test benches.
• Write test scripts using "C" and "Tcl/TK" code languages.
• Conduct functional verification and testing of new ASIC designs prior to fabrication using Field Programmable Gate Arrays (FPGA) to emulate the chips.
• Write custom interfaces between Commercial off the Shelf (COTS) software and Mentor Graphics products.
• Use advanced verification methodologies using industry standard UVM (Unified Verification Methodology).
• Perform functional testing on variants, prototype devices and production versions of ASIC chip designs following production.
• Design in-depth security verification tests.

Requirements

• Active TS/SCI w/ Polygraph
• Ten (10+) years of IA hardware testing and integration development experience
• Bachelor's degree in Engineering or Computer Science (or equivalent experience)
• Ten (10+) years of experience in programming languages: Java, Python, C/C++, RISC Assembly, Bash, Tcl/TK, and Verilog.
• Ten (10+) years of experience with GitLab, FPGA design, Xilinx's Vivado, Microblaze Design Suite, and Partial Reconfiguration.