SerDes Circuit Design Engineer

$121,900 - $183,600/Yr

Apple - Cupertino, CA

Full-time - Entry Level

Cupertino, CA

Computer and Electronic Product Manufacturing

About the position

We are seeking experienced Analog Mixed-Signal designers to join our high-speed SerDes team, specializing in building next-generation high-performance wireline transceivers for Apple's system-on-chip (SOC). This role involves collaborating with cross-functional teams to create state-of-the-art intellectual property (IP) that enhances user experience and meets high standards of quality, innovation, and efficiency.

Responsibilities

• Develop high-performance and high-speed AMS circuits used in SerDes PHY.
• Evaluate different circuit topologies for specific product requirements such as Rx, CDR, Tx, and bias generator.
• Lead discussions with multi-functional teams to create and drive block-level specifications and mixed-signal implementations.
• Work closely with SOC teams to deliver IP views and ensure quality standards are met.
• Communicate progress, discuss new ideas, and drive new implementations/concepts with peers and management.

Requirements

• BSEE with 0+ years of proven experience; Masters preferred.
• Deep understanding of AMS design with experience in high-speed serial links.
• Solid understanding of designing AMS circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters.
• Understanding of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques.
• Experience with digitally assisted analog design concepts such as background calibrations and LMS based adaptive loops.
• Proven experience working on system and architecture teams to drive block-level and IP requirements.
• Experience with high-speed digital circuits and solid understanding of digital design concepts.
• Proven understanding of Tx/Rx equalization techniques and circuits for 20+ Gbps NRZ and PAM applications.
• Experience with EQ adaptation methods and circuit interactions to improve PPA.
• Solid understanding of CDR architectures and implementations.
• Experience in Analog Mixed Signal circuit modeling and performance evaluation using SystemVerilog, Matlab, Python, VerilogAMS.
• Hands-on experience in lab testing, debugging, and data analysis.
• Experience in advanced CMOS technologies and design with FinFet technology.
• Experience with AMS IC development from definition to high-volume production.

Nice-to-haves

• Concepts of timing closure and related industry tools (e.g., Nanotime, Primetime).
• Knowledge of common high-speed SerDes protocols (e.g., PCIe, USB, DP, MPHY).
• Skills in scripting and automation to improve efficiency.

Benefits

• Comprehensive medical and dental coverage.
• Retirement benefits.
• Discounted products and free services.
• Reimbursement for certain educational expenses, including tuition.
• Discretionary bonuses or commission payments.
• Relocation assistance.