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Amazon.com - Austin, TX
posted 2 days ago
About the position
AWS Utility Computing (UC) provides product innovations that continue to set AWS's services and features apart in the industry. As a member of the UC organization, you'll support the development and management of Compute, Database, Storage, Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services. Additionally, this role may involve exposure to and experience with Amazon's growing suite of generative AI services and other cutting-edge cloud computing offerings across the AWS portfolio. Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. We are seeking an Serdes/PCIE Phy expert with role in the definition, design and validation of AWS next generation ML Chips, Cards and server integration. As a senior member of our platform development team, you will have the outstanding and meaningful opportunity to participate in the design and execution of all Serdes/PCIE topics, with the goal of creating and customized platforms that fit within AWS datacenter's world leading technology. The Serdes/PCIE PHY Expert will need to independently work with vendors, understand the settings, write/modify tests, debug and collect data.
Responsibilities
- Design and implement innovative next generation machine learning chips and servers.
- Collaborate with architects, design teams, software engineers to deliver the next generation ML chip.
- Be responsible for IP integration, 2.5D design, bring up, Characterization and validation.
- Drive the IP Integration and design of silicon and 2.5D packaging.
- Support the physical design team, review clocking and timing constraints.
- Drive cross-functional triage effort on complex functional and performance issues.
- Take the leadership role in post-silicon bring-up including test plans and execution.
- Perform system-level debug and root-cause analysis through bring-up, characterization, validation and production phase.
Requirements
- BS or MS in EE, ECE or CS.
- 7+ years of experience in Silicon development with -3+ years in SOC/IO/Subsystems.
- Deep understanding of Serdes/PCIE at the PHY and controller level including inner workings of PHY component blocks.
- Familiar with industry standard protocols such as PCIE.
- Experience with test chip characterization and testing compliance.
- Experience with post silicon testing include of shmoos including BER, PRBS, Eq settings.
- Knowledge of channel electrical and associated tuning parameters, e.g. TX PSET values, RX equalization.
- Experience Working with 3rd party IP vendors.
- Strong Firmware development skills within embedded environments.
Nice-to-haves
- Good leadership skills and ability to multi-task and thrive in a dynamic environment.
- Good communication skills and interpersonal skills.
Benefits
- Mentorship & Career Growth opportunities.
- Work/Life Balance initiatives.
- Inclusive Team Culture.
