SoC Architect - Fabric, System Cache and DRAM Controller

$170,700 - $234,400/Yr

Samsung - Mountain View, CA

Full-time - Senior

Mountain View, CA

Merchant Wholesalers, Durable Goods

About the position

The SoC Architect for Fabric, System Cache, and DRAM Controller at Samsung Research America is responsible for developing the architecture of these subsystems in next-generation SoCs. This role involves high-level performance modeling, collaboration with various engineering teams, and delivering architecture proposals that enhance performance and power efficiency for Samsung Galaxy products.

Responsibilities

• Identify and deliver Fabric, System cache and DRAM controller subsystem architecture proposals for products in new and existing markets.
• Evaluate architecture proposal benefits in collaboration with a team of SoC Architects and communicate the results across related engineering audiences (SW, HW, Architecture, Leadership).
• Perform high-level performance modeling/simulation and analysis of Fabric, System cache and DRAM controller features, applications, benchmarks, and complex use cases.
• Direct and orchestrate performance modeling and studies to support inclusion of these features in the next generation microarchitecture based on performance, area, or power improvement.
• Deliver architecture/microarchitecture proposals and specifications to the design team and articulate them effectively across audiences ranging from hardware & software engineers to architecture community peers, and to technology leadership.
• Collaborate with silicon bring-up and product teams to verify and debug the proposal and its delivered performance.
• Collaborate across teams to bring microarchitectural proposals to fruition across the SOC, Driver, OS, System through detailed documentation.

Requirements

• BSc, Masters, or PhD in Computer Science/Engineering, or equivalent combination of education, training, and experience.
• 8+ years of experience in SOC or ASIC design and architecture.
• Prior direct experience (> 7 years) in Fabric, System Cache, DRAM controller Architecture or microarchitecture is required.
• High proficiency in architecture analysis and performance modeling, ranging from simple analytical models to complex cycle accurate performance models and correlation, especially around fabric, system cache and DRAM controller.
• Ability to leverage existing simulation capabilities (GEM5, FastSIM, Platform Architect) or create new simulation capabilities when necessary.
• Detailed knowledge of ARM bus infrastructure (ACE/AXI/AHB), JEDEC standards.

Benefits

• Competitive salary ranging from $170,700 to $234,400 per year.