SoC Design/Integration & Synthesis Engineer

Apple - Cupertino, CA

Full-time - Mid Level

Cupertino, CA

Computer and Electronic Product Manufacturing

About the position

As an SOC/ASIC Integration & Synthesis Engineer at Apple, you will play a crucial role in the design and integration of System on Chip (SoC) solutions. This position involves driving all front-end integration activities, including integration, synthesis, UPF (Unified Power Format), logical equivalence checking, and engineering change orders (ECO). You will work closely with a team of engineers to improve methodologies that enhance synthesis quality of results (QOR) and optimize power, performance, and area (PPA) metrics using cutting-edge technologies. Your responsibilities will also include low power design, writing UPFs, and verifying power intent at the chip level. In this dynamic role, you will engage in RTL (Register Transfer Level) integration, manage timing constraints, and synthesize designs. Familiarity with front-end flows such as linting and logical equivalence checking (LEQ) is advantageous, as is scripting experience. Collaboration with other teams, including SOC Design, SOC Design Verification, Emulation, Static Timing Analysis (STA), Power, and Physical Design, will be essential to ensure the successful implementation of complex chips. This position offers the opportunity to work on challenges that have yet to be solved, contributing to the development of extraordinary products and services at Apple.

Responsibilities

• Drive all front-end integration activities including Integration, Synthesis, UPF, Logical Equivalence, and ECO.
• Work on methodology improvements to enhance synthesis QOR.
• Engage in low power design, writing UPFs, and verifying power intent at the chip level.
• Perform RTL integration, manage timing constraints, and synthesize designs.
• Collaborate with SOC Design, SOC Design Verification, Emulation, STA, Power, and Physical Design teams.

Requirements

• BS degree in a relevant field and a minimum of 10 years of industry experience.
• Expertise in digital design integration, synthesis, UPF, timing analysis, and closure.
• Experience in synthesis/integration of RTL and basic understanding of UPF.
• Hands-on experience in all aspects of the chip development process with proficiency in front-end tools and methodologies.
• Experience with scripting languages such as Perl, Tcl, or Python.

Nice-to-haves

• RTL logic design or implementation experience on multi-million gate ASICs.
• Ability to communicate effectively across all internal groups.
• Attention to detail and a desire to learn.

Benefits

• Health insurance coverage
• 401k retirement savings plan
• Paid holidays
• Flexible scheduling
• Professional development opportunities