SoC I/O Subsystem Design Engineer

ARM - Chandler, AZ

Full-time

Hybrid - Chandler, AZ

About the position

The SoC I/O Subsystem Design Engineer at ARM is a full-time role focused on integrating PCIe, DDR, and other IP for System on Chips (SoCs). The position requires a self-motivated design engineer with expertise in micro-architecture and logic design, who will collaborate with various teams to develop design specifications, write micro-architecture specifications, and enhance design methodologies. The role emphasizes teamwork, creativity, and the ability to guide and support team members to ensure successful project completion.

Responsibilities

• Integrate PCIe, DDR, and other IP for SoCs as part of a team.
• Understand and review architecture to develop design specifications.
• Write micro-architecture specifications and develop RTL.
• Fix bugs and run various design checks.
• Collaborate with the verification team to review test plans and debug design issues.
• Evaluate and improve I/O performance with the performance analysis team.
• Assist the backend implementation team with floor planning, writing constraints, and timing closure.
• Contribute to developing and enhancing design methodologies used by the team.
• Guide and support other team members to enable successful project activities.
• Work with Project Management on activities, plans, and schedules.

Requirements

• Bachelor's or Master's degree in Computer Science or Electrical/Computer Engineering or a related field.
• 7+ years of experience in design of complex compute subsystems or SoCs.
• Strong knowledge of digital hardware design and Verilog HDL.
• Thorough understanding of current design techniques for complex SoC development.
• Experience developing and integrating subsystems for PCIe, DDR/LPDDR, HBM, UCIe, Ethernet.
• Experience creating design specifications and developing RTL for SoC projects.
• Experience in static design checks, including CDC, RDC, X-Propagation, Linting.
• Experience with Perl, Python, or other scripting languages.

Nice-to-haves

• Experience with ARM-based designs and/or ARM System Architectures.
• Experience with SystemVerilog and verification methodologies - UVM/OVM/e.
• Experience leading small teams or projects.
• Knowledge in synthesis and timing analysis.
• Familiarity with power management techniques.
• Experience with DFT and physical implementation.

Benefits

• Hybrid working model to support work-life balance.
• Support for accommodations during the recruitment process.
• Commitment to equal opportunities and a diverse workplace.