SoC Integration Engineer

Apple - Austin, TX

Full-time - Mid Level

Austin, TX

Computer and Electronic Product Manufacturing

About the position

In this role at Apple, you will take ownership of all aspects of design and development for large System on Chips (SoCs), including SOC blocks and sub-systems. This position is critical as it involves handling both internal and external Intellectual Property (IP) integration while building sophisticated sub-systems. You will be responsible for designing the top-level SOC with various components such as IPs, sub-systems, PHY-macros, IO/PAD-ring, system bus, and other essential infrastructure components that manage clocking, reset, and power management. Your responsibilities will include developing integration specifications, conducting quality control checks to ensure the highest quality of work, creating Unified Power Format (UPF) specifications, running synthesis, generating netlists, and closing timing for the blocks. You will work closely with teams across Chip Architecture, Design Verification, Physical Design, Design for Test (DFT), and power teams to meet SOC tapeout goals on schedule. Additionally, you will develop and maintain methodologies, flows, and checks for your designs, ensuring that all designs are delivered on time and with the utmost quality by incorporating accurate checks at every stage of the design process.

Responsibilities

• Own all aspects of design and development of large SOCs, SOC blocks, and sub-systems.
• Handle internal/external IP integration and build sophisticated sub-systems.
• Design the SOC top level with IPs, sub-systems, PHY-macros, IO/PAD-ring, and other infrastructure components.
• Develop integration specifications and run quality control checks to ensure quality.
• Create UPF, run synthesis, generate netlist, and close timing for the block.
• Collaborate with Chip Architecture, Design Verification, Physical Design, DFT, and power teams to achieve SOC tapeout goals on schedule.
• Develop and maintain methodology, flows, and checks for designs.
• Work with multi-disciplinary groups to ensure designs are delivered on time and with high quality.

Requirements

• Experience working on Front-End (FE) design including RTL design, synthesis, and QC flows for large scale SOCs.
• Proven track record of working on dedicated designs in production environments for low power applications.
• Expertise in SOC IP integration, sub-system creation, and RTL Design for SOC top-level including IO/PAD-ring, clock and reset distribution, and power management.
• Experience in FE production synthesis with DFT insertion and expertise in RTL/netlist quality checks including lint, CDC, RDC, and logical equivalence.
• Extensive experience developing power intent (UPF) for complex, high-performance, and low-power SOCs with multiple power and voltage islands.
• Familiarity with DFT (scan, BIST, JATG), timing closure (STA), and backend related methodologies and tools.