SoC Performance Architect

$198,600 - $297,800/Yr

Qualcomm - Austin, TX

Full-time - Mid Level

Austin, TX

Computer and Electronic Product Manufacturing

About the position

The SoC Performance Architect at Qualcomm is responsible for creating performance and power models for server-class SoCs, focusing on components such as the fabric NoC, DRAM controller, and IO blocks. This role involves correlating models against RTL behavior, prototyping ideas, and productizing performance and power features for future SoC designs.

Responsibilities

• Develop a SoC performance/power model for blocks such as interconnect NoCs, distributed system caches, memory controllers, IO controllers.
• Verify model correctness by writing unit-tests and debugging mismatches against expectations.
• Identify ideas for improving the SoC's performance/power characteristics. Prototype idea in the performance/power model and thoroughly characterize it.
• Work with architects and RTL developers to productize the improvements identified through detailed studies.
• Conduct RTL performance verification, including creation of verification plans and directed tests/checkers.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Science, or related field and 6+ years of Systems Engineering or related work experience, OR a Master's degree with 5+ years, OR a PhD with 4+ years of experience.
• 2+ years of experience in one or more system architecture technology areas and products (e.g., Power System, Shared Resource Management, Limits/Thermal Management, Hardware Islands).
• Strong grasp of computer architecture fundamentals, especially in interconnects, traffic QoS, distributed caches, coherency flows, DRAM controller, and IO (PCIe) flows.
• Proficient in C++ and Perl/Python.
• Exposure to performance analysis and debugging.
• Ability to independently identify, troubleshoot, and solve performance problems.

Nice-to-haves

• MS in Computer Science/Computer Engineering/Electrical Engineering with 6 years of experience in CPU/SoC performance/power modeling, analysis/debug.
• Expertise in coherent fabrics based on the AMBA CHI/AXI protocol.
• Memory controller designs for LPDDR5, DDR5.
• IO controllers and fabric bridges for PCIe/CXL/CCIX.
• Strong background in building fast, accurate SoC/CPU performance models in C++.
• Exposure to testing and debugging performance issues in pre- and post-silicon environments.
• Demonstrable experience in productizing features that improve performance/power characteristics of a design.

Benefits

• Competitive annual discretionary bonus program
• Opportunity for annual RSU grants
• Comprehensive benefits package designed to support success at work, home, and play