SoC Physical Design Engineer, PnR

$143,100 - $264,200/Yr

Apple - Sunnyvale, CA

Full-time - Mid Level

Sunnyvale, CA

Computer and Electronic Product Manufacturing

About the position

At Apple, we are looking for a dedicated and passionate individual to join our team in a highly visible role responsible for the physical implementation of design partitions for a complex System on Chip (SOC). This position involves working closely with the logic design team to understand the architecture of the partitions and to drive the physical aspects early in the design cycle. You will be tasked with completing the netlist to GDS2 implementation for the partitions while ensuring that we meet our schedule and design goals. This role requires a strong focus on timing, physical, and electrical verification, as well as driving the signoff closure for the partitions. In this role, you will also be responsible for resolving and improving design and flow issues related to physical design. You will need to identify potential solutions and drive their execution to ensure the success of the project. The ideal candidate will have a strong background in partition level place and route (P&R) implementation, including floorplanning, clock and power distribution, and timing closure. You will be expected to adhere to stringent schedule and die size requirements while demonstrating strong communication skills and the ability to work collaboratively with various teams. Your experience with industry-standard tools and your understanding of their capabilities and underlying algorithms will be crucial in this role. Additionally, you should have experience with large SOC designs, particularly those exceeding 20 million gates and operating at frequencies greater than 1 GHz. This position offers a unique opportunity to contribute to groundbreaking products and services at Apple, where innovation and dedication are at the forefront of our mission.

Responsibilities

• Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.
• Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals.
• Conduct timing, physical and electrical verification and drive the signoff closure for the partitions.
• Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution.

Requirements

• Minimum BS and 3+ years of relevant industry experience.
• Knowledgeable in partition level P&R implementation including floorplanning, clock and power distribution, timing closure, and physical and electrical verification.
• Strong knowledge of physical design construction and analysis flows and methodology.
• Shown ability to adhere to stringent schedule and die size requirements.
• Strong communication skills.
• Experienced with industry standard tools, understanding their capabilities and underlying algorithms.
• Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ.

Benefits

• Comprehensive medical and dental coverage
• Retirement benefits
• Discounted products and free services
• Reimbursement for certain educational expenses including tuition
• Discretionary bonuses or commission payments
• Relocation assistance
• Opportunity to participate in Apple's discretionary employee stock programs
• Eligibility for discretionary restricted stock unit awards
• Ability to purchase Apple stock at a discount through the Employee Stock Purchase Plan