SoC Physical Design Engineer, STA/Timing

$175,800 - $312,200/Yr

Apple - Sunnyvale, CA

Full-time - Senior

Sunnyvale, CA

Computer and Electronic Product Manufacturing

About the position

At Apple, we are looking for a highly skilled individual to take on a visible role in the physical implementation of design partitions for a complex System on Chip (SoC) using state-of-the-art process technology. This position requires a deep understanding of the intricacies involved in transitioning from netlist to tapeout, ensuring that our innovative products meet the highest standards of performance and reliability. You will collaborate closely with design teams to debug constraints and facilitate necessary logic changes to enhance timing performance. Your expertise will be crucial in creating timing Engineering Change Orders (ECOs) for project tapeout, as well as in developing and maintaining scripts and methodologies for analysis and runs. Additionally, you will be responsible for creating comprehensive documentation and guidelines to support the design process. In this role, you will conduct deep analyses of timing paths to identify key issues that could impact the performance of our SoCs. Implementing timing infrastructure will be a critical part of your responsibilities, as will working with the Physical Design team to highlight issues and best practices. Your contributions will directly influence the success of our projects and the overall quality of our products, making this a pivotal position within our organization. We are looking for someone who is not only technically proficient but also a good communicator, capable of accurately describing issues, proposing effective solutions, and driving them through to completion.

Responsibilities

• Work with design teams to understand and debug constraints, facilitating logic changes to improve timing.
• Collaborate with the Physical Design team to highlight issues and best practices.
• Create timing ECOs for project tapeout.
• Develop and maintain scripts and methodologies for analysis and runs.
• Create documentation and help with guidelines/specs.
• Conduct deep analysis of timing paths to identify key issues.
• Implement timing infrastructure.

Requirements

• Minimum BS degree and 10+ years of relevant industry experience.
• Familiarity with all aspects of timing of large high-performance SoC designs in sub-micron technologies.
• Expertise in Static Timing Analysis (STA) and methodologies for timing closure, with a deep understanding of noise, crosstalk, and OCV effects.
• Familiarity with circuit modeling including SPICE models and worst-case corner selection.
• Strong programming skills in Perl and TCL.
• Experience with large design STA and Timing Closure.
• Expertise in ECO techniques and implementation.
• Good communication skills to accurately describe issues, propose solutions, and drive them through completion.

Benefits

• Comprehensive medical and dental coverage
• Retirement benefits
• Discounted products and free services
• Reimbursement for certain educational expenses, including tuition
• Discretionary bonuses or commission payments
• Relocation assistance
• Participation in Apple's discretionary employee stock programs
• Opportunity to purchase Apple stock at a discount through the Employee Stock Purchase Plan