SOC Design Engineer, Senior Staff

About the position

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. As a SOC Physical Design Engineer, Senior Staff, you are a seasoned professional with a deep understanding of the full SOC design cycle, particularly focusing on physical design. You are proficient in Synopsys tools and have a strong track record of delivering high-quality tape-outs. You excel in a collaborative environment, working well with cross-functional teams to meet SOC development objectives. Your experience spans various technology nodes, and you are adept at managing complex IP sub-systems. You bring a proactive approach, recognizing and mitigating risks while ensuring high standards of quality. Your ability to obtain government security clearances is preferred, as this role involves working on Aerospace and Government customer SOC programs.

Responsibilities

• Implementing SOC physical design from RTL to GDSII.
• Working on SOC top-level and block-level physical design implementation and design closure.
• Developing and improving methodologies and flows within Synopsys and customer environments.
• Collaborating with customer teams, acting as an extension of their design team.
• Managing top-level floor-planning, bump-maps, RDL IO Pad/Ring creation/verification, and power grid creation/verification.
• Defining sign-off requirements and margins based on Foundry technology requirements.

Requirements

• BS or MS with 10+ years of experience in SOC physical design.
• Proficiency with Synopsys tools such as DC, DCG, DC TOPO, Fusion Compiler/ICC2, and Lynx.
• Experience with top-level floor-planning, clocking methodologies, and power grid creation/verification.
• Understanding of DFT structures, formal verification, and UPF flows.
• Experience with GlobalFoundries, TSMC, and Samsung technology nodes.

Benefits

• Comprehensive health, wellness, and financial benefits.
• Annual bonus eligibility.
• Equity and other discretionary bonuses.