Sr. Coherent Interconnect Micro-architect/Logic Designer

$174,557 - $305,414/Yr

Samsung Electronics America - San Jose, CA

Full-time - Senior

Hybrid - San Jose, CA

Merchant Wholesalers, Durable Goods

About the position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!

Responsibilities

• Drive the timely development of custom coherent interconnect IP and/or last level cache (LLC) blocks.
• Engage with the architects and help define next-generation Samsung coherent interconnects and LLC.
• Perform microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specification.
• Work with the verification team to verify the functionality and correctness of the design.
• Collaborate with implementation to achieve timing and area goals.
• Produce quality RTL on schedule meeting PPA goals.
• Engage with performance and power team on achieving performance and power goals.
• Partner with the physical design and CAD team to resolve implementation level details.
• Help mentor junior engineers in the team.

Requirements

• 15+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 13+ years of experience with a Master's degree, or 11+ years of experience with a PhD.
• Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for high performance digital designs.
• Demonstrated experience of successful Architectural through RTL design experience on high performance digital designs.
• Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
• Knowledge of system caches and directory snoop filter protocols.
• Familiarity with different on-chip network topologies: mesh, ring, crossbar.
• Experience in leading and mentoring a team of engineers.
• Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols.
• Knowledge of memory subsystem design including coherent cache design.
• Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.

Nice-to-haves

• Knowledge of Verilog/VHDL, scripting, STA, DFT, ECO flows.
• Proficient in AMBA, ACE, AXI, CHI protocols.
• Knowledge of memory controller and either coherent interconnect or cache design.
• Knowledge of memory subsystem, coherency, directory snoop filter protocols.
• Familiarity with different on-chip network topologies: mesh, ring, crossbar.
• Experience with a scripting language like Perl or Python.
• Energetic, curiosity, and passion in logic design.
• Good written and verbal communication skills.
• Efficient digital design techniques.

Benefits

• Medical, dental, vision, life insurance.
• 401(k).
• Free onsite lunch.
• Employee purchase program.
• Tuition assistance (after 6 months).
• Paid time off.
• Student loan program.
• Wellness incentives.
• MBO bonus compensation based on company, division, and individual performance.
• Eligibility to participate in long term incentive plan and relocation.