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Sr. Design Verification Engineer (Coherent Interconnect)
Samsung Electronics America - San Jose, CA
posted 3 days ago
About the position
Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!
Responsibilities
- Contribute to the functional verification of System IP including coherent interconnect, caches, and dynamic memory controllers.
- Act as the go-to person for technical know-how and micro architecture.
- Architect and build re-usable testbenches right from scratch.
- Identify shortcomings of existing verification flows and propose new solutions.
- Propose and drive best practices and methodologies that can improve productivity.
- Own key features and timely execution of tasks as per milestones.
- Create test plans as per spec, challenge spec and testplan/code reviews.
- Work with designers to resolve any spec issues.
- Create verification environments, stimulus, and tests.
- Collaborate with designers to verify the correctness of a design feature and resolve fails.
- Develop assertions, checkers, covergroups, and Systemverilog constraints.
- Debug and root cause functional fails from regressions.
- Analyze code and functional coverage results and perform gap analysis.
- Identify coverage exclusions and improve stimulus.
- Work with SoC team to debug functional fails during IP bringup and feature execution.
- Collaborate with Physical design teams, running and debugging gate-level simulations.
- Work with Performance verification teams to help with co-sim TB bringup.
- Bringup power-aware verification with UPF.
- Help with Silicon bringup and root causing fails.
- Mentor junior team members.
Requirements
- 20+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 18+ years of experience with a Master's degree, or 16+ years of experience with a PhD.
- 16+ years industry experience in a design verification role.
- Expert hands-on coding skills in System Verilog, UVM.
- Knowledge of ARM protocols - CHI, AXI, ACElite, APB.
- Experience with Git version control, Unix/Perl scripting.
- Combined experience with coherent interconnect and LPDDR memory controllers will be a plus.
- Good written and verbal communication skills.
- Formal verification skills will be a plus.
Benefits
- Medical insurance
- Dental insurance
- Vision insurance
- Life insurance
- 401(k)
- Free onsite lunch
- Employee purchase program
- Tuition assistance (after 6 months)
- Paid time off
- Student loan program
- Wellness incentives
- MBO bonus compensation based on performance
- Long term incentive plan eligibility
- Relocation assistance
