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Sr. Design Verification Engineer (Memory Controller)
Samsung Electronics America - San Jose, CA
posted 3 days ago
About the position
Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!
Responsibilities
- Architect and build re-usable testbenches right from scratch
- Propose and drive best practices/methodologies/automation that can improve productivity
- Own key features and timely execution of tasks as per milestones
- Create test plans as per spec and present to various stakeholders
- Work with designers to resolve any spec issues
- Collaborate with designers to verify the correctness of a design feature, and resolve fails
- Develop assertions, checkers, covergroups, Systemverilog constraints
- Analyze and debug, root causing functional fails from regressions
- Perform coverage gap analysis, identifying coverage exclusions and improving stimulus
- Integrate memory models (VIP) from vendors into TB and bringup
- Develop fake PHY models and bringup, and bringing up real PHY
- Verify DRAM interface training, Link ECC/EDC, Command/WR/RD paths, Schedulers, DVFS, Power Down, Self-Refresh
- Work with SoC team to debug functional fails during IP bringup and feature execution
- Collaborate with Performance Verification teams to help with co-sim TB bringup
- Help with Silicon bringup and root causing fails
- Mentor junior team members, work independently, and are a team player
Requirements
- 15+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 13+ years of experience with a Master's degree, or 11+ years of experience with a PhD
- 15+ years industry experience in a design verification role
- Expert hands-on coding skills in Testbench, Stimulus, checker development & coverage closure
- Experience with System Verilog, UVM or equivalent
- Experience with LPDD5/5X/6 memory model VIPs
- Experience with DDR/LPDDR/HBM protocols
- Experience with Git version control, Unix/Perl/Python scripting
- Combined experience with coherent interconnect, caches, and LPDDR memory controllers is highly preferred
- Formal verification skills will be a plus
- Good written and verbal communication skills
Benefits
- Medical insurance
- Dental insurance
- Vision insurance
- Life insurance
- 401(k)
- Free onsite lunch
- Employee purchase program
- Tuition assistance (after 6 months)
- Paid time off
- Student loan program
- Wellness incentives
- MBO bonus compensation based on performance
- Eligibility for long term incentive plan
- Relocation assistance
